Inventors:
Robert Ruiz - Sunnyvale CA
Hari Ganesan - Fremont CA
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G01R 3128
Abstract:
In a computer implemented synthesis system, a method of generating a test program for use in testing device with ATE (automated test equipment). The computer implemented steps of receiving an HDL specification representing a design to be realized in physical form and storing the HDL specification in a computer memory unit, receiving constraints applicable to the design, and compiling the HDL specification with a compiler to produce a netlist description of the design, wherein the netlist comprises functional logic blocks and connections there between, including sequential cells and combinational logic. The netlist is a scan-based sequential circuit netlist having multiple, skewed capture events. Combinational circuit analysis is then performed on the sequential logic netlist. The netlist is then processed to transform the netlist to a combinational logic netlist.