US Patent:
20170302440, Oct 19, 2017
Inventors:
- San Jose CA, US
Gangesh Kumar Ganesan - Mountain View CA, US
International Classification:
H04L 9/06
H04L 9/32
Abstract:
Technology, implemented in digital hardware, software, or combination thereof, for completing Secure Hash Algorithm (SHA-2) computation with generating one new hash value at each clock cycle is described. The technology includes: using synchronous logic to store the computed values every alternate clock and combinational logic to process multiple rounds of SHA in each clock; completing hash calculation in unrolled modes; using efficient adders for most 32-bit adders to improve performance.