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Mira Ben-Tzur

from Sunnyvale, CA
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Related to:
Ran D Bentzur, 38Mira Ben Bentzur, 66Ran Ben-Tzur, 38Tzvi Tzur, 70Dana Bentzur, 35Mira Bentzur
Connected to:
Nitza Ben-Yehuda, 81Raanan Ben-Zur, 73Kfir N Ben-Zvi, 48Alicia E Bena, 35Jack L Bena, 85Lisa M Bena, 55Piyush M Bena, 47Sarah A Bena, 39Thomas R Bena, 97Karim Benabdallah, 52

Mira Ben-Tzur Phones & Addresses

  • 1567 Kingsgate Dr, Sunnyvale, CA 94087

Publications

Us Patents

Borderless Contact Architecture

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US Patent:
6713831, Mar 30, 2004
Filed:
Dec 4, 2001
Appl. No.:
10/010837
Inventors:
Sharmin Sadoughi - Cupertino CA
Mira Ben-Tzur - Sunnyvale CA
Michal E. Fastow - Cupertino CA
Saurabh Dutta Chowdhury - Belmont CA
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H01L 310232
US Classification:
257437, 257436, 257760
Abstract:
A method and a system are provided for forming a borderless contact structure. In particular, a method is provided which includes using an inorganic anti-reflective coating layer as an etch stop to form a borderless contact structure. In some embodiments, the method may include patterning an interconnect line above an inorganic layer with anti-reflective properties and depositing an upper interlevel dielectric layer above the interconnect line. A trench may then be etched within the upper interlevel dielectric layer such that a borderless contact structure may be formed in contact with said interconnect line. Consequently, a semiconductor topography is provided, in such an embodiment, which includes an inorganic anti-reflective coating layer arranged below an interconnect line and a contact structure arranged upon the interconnect line. In some embodiments, a width of the contact structure may be greater than a width of the interconnect line.

Metal Stack For Local Interconnect Layer

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US Patent:
6774033, Aug 10, 2004
Filed:
Nov 4, 2002
Appl. No.:
10/287258
Inventors:
Mira Ben-Tzur - Sunnyvale CA
Dafna Beery - Palo Alto CA
Gorley L. Lau - Fremont CA
Krishnaswamy Ramkumar - San Jose CA
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 214763
US Classification:
438643, 438685, 438627
Abstract:
In one embodiment, a local interconnect layer in an integrated circuit is formed by depositing a first film over an oxide layer and depositing a second film over the first film. The first film may comprise titanium nitride, while the second film may comprise tungsten, for example. The first film and the second film may be deposited in-situ by sputtering. The second film may be etched using the first film as an etch stop, and the first film may be etched using the oxide layer as an etch stop.

Method Of Forming A Floating Metal Structure In An Integrated Circuit

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US Patent:
6835616, Dec 28, 2004
Filed:
Jan 29, 2002
Appl. No.:
10/059823
Inventors:
Mira Ben-Tzur - Sunnyvale CA
Krishnaswamy Ramkumar - San Jose CA
James Hunter - Campbell CA
Thurman J. Rodgers - Woodside CA
Mike Bruner - Saratoga CA
Klyoko Keuchi - Sunnyvale CA
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 218242
US Classification:
438244, 438253
Abstract:
In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.

Integrated Circuit With Improved Rc Delay

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US Patent:
6841878, Jan 11, 2005
Filed:
Sep 26, 2003
Appl. No.:
10/672895
Inventors:
Mira Ben-Tzur - Sunnyvale CA, US
Krishnaswamy Ramkumar - San Jose CA, US
Alain Blosse - Belmont CA, US
Fuad Badrieh - Santa Clara CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 2348
US Classification:
257750, 257758, 257760
Abstract:
In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

Reticle Repeater Monitor Wafer And Method For Verifying Reticles

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US Patent:
6844235, Jan 18, 2005
Filed:
Jul 31, 2001
Appl. No.:
09/920374
Inventors:
Christopher M. Jones - San Francisco CA, US
Mira Ben-Tzur - Sunnyvale CA, US
Allen Fung - San Francisco CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 2176
H01L 21301
H01L 2144
H01L 21461
US Classification:
438401, 438462, 438612, 438653, 438656, 438720, 438945
Abstract:
According to one embodiment, verifying a reticle may include patterning an inspected layer (-) according to a reticle pattern, depositing a contrast enhancing layer (-) on a patterned layer (-), and inspecting a reticle patterned formed in the inspected layer (-).

Low-K Dielectric Layer With Air Gaps

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US Patent:
6903002, Jun 7, 2005
Filed:
Sep 11, 2002
Appl. No.:
10/241236
Inventors:
Mira Ben-Tzur - Sunnyvale CA, US
Krishnaswamy Ramkumar - San Jose CA, US
Christopher A. Seams - Pleasanton CA, US
Thurman J. Rodgers - Woodside CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L021/4763
H01L021/302
US Classification:
438622, 438623, 438624, 438631, 438633, 257752, 257758
Abstract:
In one embodiment, a metal level includes a plurality of metal lines. A low-k dielectric is deposited over the metal level such that an air gap forms at least between two metal lines. The relatively low dielectric constant of the low-k dielectric reduces capacitance on metal lines regardless of whether an air gap forms or not. The air gap in the low-k dielectric further reduces capacitance on metal lines. The reduced capacitance translates to lower RC delay and faster signal propagation speeds.

Method Of Making Borderless Contacts In An Integrated Circuit

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US Patent:
6911395, Jun 28, 2005
Filed:
Sep 22, 2000
Appl. No.:
09/668604
Inventors:
Jiamin Qiao - Fremont CA, US
Mira Ben-Tzur - Sunnyvale CA, US
Prabhuram Gopalan - Fremont CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L021/302
US Classification:
438689, 438700, 438704, 438710, 438720, 438724
Abstract:
According to one embodiment (), a method of forming borderless contacts may include forming a composite layer over a first insulating layer (). A contact hole may be formed through a composite layer and a first insulating layer (). A conducting layer may then be formed (), including within a contact hole. Portions of a conducting layer may then be removed with a composite layer as a polish stop (), and a contact structure may be formed. A first interconnect structure and a second insulating layer may then be formed over a first insulating layer (and ). A borderless contact pattern may then be etched with a composite layer as an etch stop ().

Low-K Dielectric Layer With Overlying Adhesion Layer

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US Patent:
6939792, Sep 6, 2005
Filed:
Mar 28, 2003
Appl. No.:
10/402865
Inventors:
Maryam Jahangiri - Sunnyvale CA, US
Mira Ben-Tzur - Sunnyvale CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L021/469
H01L023/522
US Classification:
438624, 438763, 438790, 438958, 257760
Abstract:
In one embodiment, a method of fabricating an integrated circuit includes forming a low-k dielectric layer over metal lines, forming an adhesion layer over the low-k dielectric layer, and forming a capping layer over the adhesion layer. The low-k dielectric may comprise SiLK™ dielectric material, while the capping layer may comprise TEOS. The resulting stack of dielectric materials may be employed in a passivation level to protect the metal lines. For example, a topside layer may be formed over the capping layer.
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Mira Ben-Tzur from Sunnyvale, CA Get Report