Raanan Ben-Zur

6633573, Oct 14, 2003

Sep 15, 2000

09/663260

Raanan Ben-Zur - Campbell CA
Sandra Maria Frazier - Union City CA

Ciena Corporation - Linthicum MD

H04L 522

370405, 370539, 370541, 711104

A method and apparatus for generating massive interrupts in random access memory (RAM) are provided, comprising receiving and storing Time Slot network (TS Net) data frames comprising switching event information in a first RAM area. Compare operations are performed among prespecified ones of the TS Net data frames. Unit interrupt bits are set in a corresponding location of a second RAM area in response to detected bit differences resulting from the compare operations. Interrupt status bits are set in a corresponding location of a third RAM area in response to set unit interrupt bits. Massive interrupt signals are generated in response to set unit interrupt bit.

6754174, Jun 22, 2004

Sep 15, 2000

09/662697

Raanan Ben-Zur - Campbell CA
Steven L. Shepherd - Monte Sereno CA
Boris Reynov - Cupertino CA
Bayne G. Steele - Pleasanton CA
Nicholas A. Balatoni - Santa Clara CA

Ciena Corporation - Linthicum MD

H04L 2154

370225, 370466

An interface for communications among network elements of at least one network is provided, comprising at least one transmitter, at least one receiver, at least one processor, and at least one backplane coupled among the network elements. Data frames of a second type, or Time Slot Network (TS Net) data frames, are generated and transferred over the backplane in response to receipt data frames of a first type from the network. The TS Net data frames comprise switching event information. Compare operations are performed among prespecified TS Net data frames at prespecified intervals, and at least one interrupt signal is generated in response to data changes determined by the compare operations. Information routing is controlled over the network by a processor in response to the interrupt signal.

6785766, Aug 31, 2004

Sep 15, 2000

09/663509

Raanan Ben-Zur - Campbell CA
Rohit Jindal - Sunnyvale CA
Aurelio Marquez Rios - San Jose CA

Ciena Corporation - Linthicum MD

H04L 522

711104, 370539, 370541, 370405

A method and apparatus for servicing massive interrupts in random access memory (RAM) are provided, comprising receiving a massive interrupt signal, and reading at least one unit interrupt register in a first RAM area in response to the massive interrupt signal. A set unit interrupt bit corresponds to an address in a second RAM area. Interrupt status registers are read at the corresponding address in the second RAM area in response to the set unit interrupt bit. A set interrupt status bit corresponds to an address in a third RAM area. Interrupt cause bits are read at the corresponding address in the third RAM area in response to the set interrupt status bit, and detailed information is obtained about the interrupt. The interrupt is serviced in accordance with the detailed information.

6865148, Mar 8, 2005

Sep 15, 2000

09/663512

Raanan Ben-Zur - Campbell CA, US
Steven L. Shepherd - Monte Sereno CA, US
Boris Reynov - Cupertino CA, US
Bayne G. Steele - Pleasanton CA, US
Nicholas A. Balatoni - Santa Clara CA, US

Ciena Corporation - Linthicum MD

G01R031/08

370218, 370540

A method for routing network switching information includes generating at one Time Slot Network (TS Net) data firame from at least one data frame of a first type. The TS Net data frame comprises switching event information. The TS Net data frame is transferred and stored among a number of network elements using a backplane network. Compare operations are performed among prespecified data frames of the TS Net data frame, and at least one interrupt signal is generated in response to detected changes resulting from the compare operations. Information routing is controlled in at least one network and the associated network elements in response to the interrupt signals.

6920105, Jul 19, 2005

Sep 15, 2000

09/662681

Raanan Ben-Zur - Campbell CA, US
Boris Reynov - Cupertino CA, US
Bayne G. Steele - Pleasanton CA, US
Ohm P. Mishra - Fremont CA, US

CIENA Corporation - Linthicum MD

H04L021/54

370225, 370466, 370538, 709200

An interface receiver coupled among a plurality network elements of at least one network is provided, comprising at least one random access memory (RAM) and at least one comparator. Time slot network (TS net) data frames comprising switching event information are received from each of a number of channels of a backplane network. Compare operations are performed at prespecified intervals among at least one data frame stored in the RAM and at least one subsequently received data frame. Interrupt signals are generated in response to data changes determined by the compare operations.

6980568, Dec 27, 2005

Jul 17, 2001

09/906990

Boris Reynov - Cupertino CA, US
Raanan Ben-Zur - Campbell CA, US
Nicholas A. Balatoni - Santa Clara CA, US

Ciena Corporation - Linthicum MD

H04J003/06

370503, 370219

According to one embodiment, a method is disclosed. The method comprises receiving a first set of clock signals from a first clock unit at a second clock unit whenever the first clock unit is operating. The method further includes receiving a signal indicating that the second clock unit is to enter into the operating mode; and entering a holdover mode at a protection timing unit within the second clock unit. In the holdover mode, the protection timing unit generates output clock signals based upon the first set of clock signals received from the first clock unit at the second clock unit.

7054324, May 30, 2006

Sep 15, 2000

09/663511

Raanan Ben-Zur - Campbell CA, US
Avinish Kumar Sharma - Fremont CA, US

CIENA Corporation - Linthicum MD

H04L 12/56

370404, 370222, 370465

An interface transmitter coupled among a number of network elements of at least one network is provided, wherein a number of data frames of a first type are received from at least one processor and stored in at least one random access memory (RAM). Data is read from the RAM to at least one data serializer in response to a number of signals received from the processor and over at least one backplane network. A number of data frames of a second type corresponding to the data frames of a first type are generated and serially transferred among the network elements using the backplane network.

55507107, Aug 27, 1996

Sep 9, 1994

8/303318

Uriel Rahamim - Palo Alto CA
Randy Minobe - San Jose CA
Ahmad A. Chahrour - Santa Clara CA
Raanan Ben-Zur - Campbell CA

Hitachi Computer Products (America), Inc. - Santa Clara CA

H05K 714
G06F 1300

361687

A housing and cooling structure for a personal processor module (PPM) is provided which includes a case which is sealed and will fit within both a desktop sized docking station and a smaller notebook sized docking station. Within the case, the components which make up the PPM are located in such a way as to minimize the size of the printed circuit boards. In addition, a cooling mechanism is provided which cools all of the components within the case. Also, the PPM has structure for converting 3. 3 volt signals into 5 volt signals and for permitting easy upgrades.