Yasunobu Kosa

53451058, Sep 6, 1994

Aug 2, 1993

8/103362

Shih-Wei Sun - Austin TX
Yasunobu Kosa - Austin TX
John R. Yeargain - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2334
H01L 2504

257659

A shielding structure (10) and method of formation. The shielding structure (10) has a substrate (12). A first dielectric layer (14) overlies the substrate (12). A conductive layer (16) is formed overlying the dielectric layer (14), is patterned, and is etched to form electrically isolated conductive regions from conductive layer (16). The electrically isolated conductive regions have sidewalls and the etching of conductive layer (16) exposes portions of dielectric layer (14). The exposed portions of dielectric layer (14) are etched to form trenched portions of dielectric layer (14). A second dielectric layer (18) is formed overlying the electrically isolated conductive regions, including the sidewalls, and overlying the trenched portions to create recessed regions that separate the electrically isolated conductive regions. A shielding conductive layer (20) is formed overlying dielectric layer (18) and at least partially fills the recessed regions to shield the electrically isolated conductive regions from each another.

52143015, May 25, 1993

Jun 29, 1992

7/906172

Yasunobu Kosa - Austin TX
W. Craig McFadden - Austin TX
Keith E. Witek - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2976

257329

A field effect transistor having regions (20, 20', and 20") which respectively function as a planar elevated surface for gate, drain, and source electrical contact, and method of fabrication. The transistor overlies a substrate (12) and is formed partially from active areas (14 and 14'). The regions (20, 20', and 20"), each underlie or are surrounded by a dielectric layer (22). A gate is formed by a gate layer (24). A source (30) is formed within region (20") and is electrically connected to active area (14'). A drain (30') and channel region are formed within region (20'). Electrical contact is made to the source (30), drain (30') and gate layer (24) by conductive layers (34", 34', and 34, respectively).

53648102, Nov 15, 1994

Jul 28, 1992

7/921039

Yasunobu Kosa - Austin TX
Howard C. Kirsch - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2170
H01L 2700

437 52

The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a static random access memory cell (110) having a vertical n-channel field-effect transistor (116) and a vertical p-channel field-effect transistor (115) and methods of forming them. In one embodiment, a six-transistor static random access memory cell (110) has two pass transistors (111 and 114), which are planar n-channel field-effect transistors, two latch transistors (113 and 116), which are vertical n-channel field-effect transistors with drain regions having graded diffusion junctions (31), and two load transistors (112 and 115), which are vertical p-channel thin-film field-effect transistors having laterally recessed channel regions (92).

52623530, Nov 16, 1993

Feb 3, 1992

7/829837

Shih-Wei Sun - Austin TX
Yasunobu Kosa - Austin TX
John R. Yeargain - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2144
H01L 2148

437195

A shielding structure (10) and method of formation. The shielding structure (10) has a substrate (12). A first dielectric layer (14) overlies the substrate (12). A conductive layer (16) is formed overlying the dielectric layer (14), is patterned, and is etched to form electrically isolated conductive regions from conductive layer (16). The electrically isolated conductive regions have sidewalls and the etching of conductive layer (16) exposes portions of dielectric layer (14). The exposed portions of dielectric layer (14) are etched to form trenched portions of dielectric layer (14). A second dielectric layer (18) is formed overlying the electrically isolated conductive regions, including the sidewalls, and overlying the trenched portions to create recessed regions that separate the electrically isolated conductive regions. A shielding conductive layer (20) is formed overlying dielectric layer (18) and at least partially fills the recessed regions to shield the electrically isolated conductive regions from each another.

50069098, Apr 9, 1991

Oct 30, 1989

7/429952

Yasunobu Kosa - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2978

357 236

A dynamic random access memory array is formed using vertical transistors and capacitors. The capacitor for each memory cell has one electrode formed in a lower region of a pillar and a second electrode in a conductive fill surrounding the lower region of the pillar. The transistor of each cell has its source, drain, and channel also formed in a single pillar. The gate of each cell is a conductive layer surrounding the channel. The conductive layer is above and insulated from the conductive fill. The conductive layer is also conveniently the word line which continuously extends from one cell in a particular row to the next cell of that row. Contact to the cell is made to the top of the pillar which is doped to the same type as that of the lower region of the pillar. The areas between the pillars is filled with insulating material but the top of the pillar is exposed. Metal bit lines are thus conveniently formed in contact with the top of the pillar which is the input/output for the cell.

49944045, Feb 19, 1991

Aug 28, 1989

7/399670

David Y. Sheng - Austin TX
Yasunobu Kosa - Austin TX
Andrew J. Urquhart - Pflugerville TX
Mark J. Cullen - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 21312
H01L 21265

437 44

A process is disclosed for the formation of an LDD structure in an MOS transistor having a reduced mask count and providing high integrity source/drain junctions. In accordance with one embodiment of the invention an MOS transistor is formed having a gate dielectric overlying an active region of the substrate. A transistor gate is formed in a central portion of the active region and an oxidation layer is formed over the active region and the transistor gate. A lightly-doped source/drain region is formed which is self aligned to the transistor gate. A conformal layer of an oxygen reactive material is formed overlying the transistor gate and the active region. The oxygen reactive material is anisotropically etched in a oxygen plasma reactive ion etch to form a sidewall spacer on the edge the transistor gate. The oxygen reactive ion etch does not penetrate the oxidation layer overlying the active region. A heavily-doped source/drain region is formed which is self aligned to the edge of the sidewall spacer.

57395640, Apr 14, 1998

Jun 1, 1995

8/460605

Yasunobu Kosa - Austin TX
Howard C. Kirsch - Austin TX
Thomas F. McNelly - Austin TX
Frank Kelsey Baker - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 21265
H01L 2170

257298

A static-random-access memory cell comprising floating node capacitors is disclosed. In one embodiment, the storage nodes acts as the first plates for the floating node capacitors, and a conductive member acts as the second plates for the floating node capacitors. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cell. In another embodiment, a conductive member acts as the second plates of a plurality of memory cells. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cells. Processes for forming the memory cells is also disclosed.

51262851, Jun 30, 1992

Jul 2, 1990

7/546974

Yasunobu Kosa - Austin TX
John H. Sweeney - Austin TX
Scott S. Roth - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 21283
H01L 21225

437191

A buried contact in a semiconductor device is formed by forming an oxide layer on a surface of a semiconductor substrate. A heavily-doped polysilicon layer is formed over the oxide layer and selectively etched to leave a first portion of the polysilicon layer over the surface and remove a second portion of the polysilicon layer from over the surface. The remaining first portion of polysilicon has a vertical surface which is over the surface of the substrate. After this step there is oxide between the first portion of the polysilicon layer and the substrate. An isotropic etch is performed which removes a portion of the oxide between the first portion of the polysilicon layer and the substrate to leave a void between the first portion of the polysilicon layer and the surface of the substrate from the vertical surface of the first portion of the polysilicon to a predetermined distance from the vertical surface of the first portion of the polysilicon layer. A polysilicon layer is then deposited which fills the void with polysilicon. The polysilicon which is not filling the void is removed.