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Yasuaki Hagiwara

from Newark, CA
Age ~61
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Also known as:
Hagi Ma
Phone and address:
5247 Sussex Pl, Newark, CA 94560
(510) 494-9066
Connected to:
Kumiko Hagiwara, 62Masato Hagiwara, 41Mike Y Hagiwara, 42Matthew S Hagiya, 66Jaclyn Hagl, 46Michael J Hagl, 58Anders Hagland, 60Robert L Hagland, 52Ronald E Hagland, 77Bob Hagle, 42

Yasuaki Hagiwara Phones & Addresses

  • 5247 Sussex Pl, Newark, CA 94560 (510) 494-9066
  • Santa Clara, CA
  • Los Angeles, CA
  • Redwood City, CA
  • Fremont, CA
  • 5247 Sussex Pl, Newark, CA 94560 (510) 908-0795

Work

Position: Professional/Technical

Education

Degree: High school graduate or higher

Emails

h***[email protected]

Resumes

Resumes

Yasuaki Hagiwara Photo 1

Design Manager

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Location:
San Francisco, CA
Industry:
Computer Networking
Work:
Netgear
Design Manager
Education:
Chiba University
Skills:
Linux
Embedded Systems
Device Drivers
Ethernet
Tcp/Ip
Security
Wireless
Debugging
Perl
Software Development
Embedded Software
Firmware
Javascript
Software Engineering
Yasuaki Hagiwara Photo 2

Design Manager At Netgear

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Location:
San Francisco Bay Area
Industry:
Computer Networking

Business Records

Name / Title
Company / Classification
Phones & Addresses
Yasuaki Hagiwara
Visco Systems, LLC
Computer Software Design
25 King St, Redwood City, CA 94062

Publications

Us Patents

Microprocessor Architecture Capable Of Supporting Multiple Heterogeneous Processors

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US Patent:
6611908, Aug 26, 2003
Filed:
Jun 21, 2001
Appl. No.:
09/884943
Inventors:
Derek J. Lentz - Los Gatos CA
Yasuaki Hagiwara - Santa Clara CA
Te-Li Lau - Palo Alto CA
Cheng-Long Tang - San Jose CA
Le Trong Nguyen - Monte Sereno CA
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
G06F 1314
US Classification:
712 29, 710243, 710317
Abstract:
A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

High-Performance, Superscalar-Based Computer System With Out-Of-Order Instruction Execution

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US Patent:
6647485, Nov 11, 2003
Filed:
May 10, 2001
Appl. No.:
09/852293
Inventors:
Le Trong Nguyen - Monte Sereno CA
Derek J. Lentz - Los Gatos CA
Yoshiyuki Miyayama - Santa Clara CA
Sanjiv Garg - Freemont CA
Yasuaki Hagiwara - Santa Clara CA
Johannes Wang - Redwood City CA
Te-Li Lau - Palo Alto CA
Quang H. Trang - San Jose CA
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
G06F 930
US Classification:
712 23, 712206, 712207, 712245, 712219, 711169
Abstract:
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

High-Performance, Superscalar-Based Computer System With Out-Of-Order Instruction Execution

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US Patent:
6915412, Jul 5, 2005
Filed:
Oct 30, 2002
Appl. No.:
10/283106
Inventors:
Le Trong Nguyen - Monte Sereno CA, US
Derek J. Lentz - Los Gatos CA, US
Yoshiyuki Miyayama - Santa Clara CA, US
Sanjiv Garg - Freemont CA, US
Yasuaki Hagiwara - Santa Clara CA, US
Johannes Wang - Redwood City CA, US
Te-Li Lau - Palo Alto CA, US
Quang H. Trang - San Jose CA, US
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
G06F015/76
G06F013/40
G06F009/38
G06F013/36
US Classification:
712 23, 712206, 712207, 712215, 712213, 712233, 712237, 712238, 712248, 712 41, 711125, 710 52, 710310
Abstract:
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

High-Performance, Superscalar-Based Computer System With Out-Of-Order Instruction Execution

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US Patent:
6934829, Aug 23, 2005
Filed:
Oct 31, 2003
Appl. No.:
10/697257
Inventors:
Le Trong Nguyen - Monte Sereno CA, US
Derek J. Lentz - Los Gatos CA, US
Yoshiyuki Miyayama - Santa Clara CA, US
Sanjiv Garg - Freemont CA, US
Yasuaki Hagiwara - Santa Clara CA, US
Johannes Wang - Redwood City CA, US
Te-Li Lau - Palo Alto CA, US
Quang H. Trang - San Jose CA, US
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
G06F009/38
G06F009/40
US Classification:
712 23, 712215, 712219, 712234, 712245, 711125
Abstract:
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

High-Performance, Superscalar-Based Computer System With Out-Of-Order Instruction Execution

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US Patent:
6941447, Sep 6, 2005
Filed:
Nov 5, 2003
Appl. No.:
10/700520
Inventors:
Derek J. Lentz - Los Gatos CA, US
Yoshiyuki Miyayama - Santa Clara CA, US
Sanjiv Garg - Freemont CA, US
Yasuaki Hagiwara - Santa Clara CA, US
Johannes Wang - Redwood City CA, US
Te-Li Lau - Palo Alto CA, US
Quang H. Trang - San Jose CA, US
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
G06F009/38
G06F013/40
US Classification:
712 23, 712215, 712219, 712234, 712245, 712218, 711138, 710305, 710316
Abstract:
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

High-Performance, Superscalar-Based Computer System With Out-Of-Order Instruction Execution

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US Patent:
6948052, Sep 20, 2005
Filed:
Oct 29, 2002
Appl. No.:
10/282207
Inventors:
Le Trong Nguyen - Monte Sereno CA, US
Derek J. Lentz - Los Gatos CA, US
Yoshiyuki Miyayama - Santa Clara CA, US
Sanjiv Garg - Freemont CA, US
Yasuaki Hagiwara - Santa Clara CA, US
Johannes Wang - Redwood City CA, US
Te-Li Lau - Palo Alto CA, US
Quang H. Trang - San Jose CA, US
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
G06F009/40
G06F013/16
US Classification:
712207, 712213, 712233, 710 52
Abstract:
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Microprocessor Architecture Capable Of Supporting Multiple Heterogeneous Processors

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US Patent:
6954844, Oct 11, 2005
Filed:
Jun 2, 2003
Appl. No.:
10/449018
Inventors:
Derek J. Lentz - Los Gatos CA, US
Yasuaki Hagiwara - Santa Clara CA, US
Te-Li Lau - Palo Alto CA, US
Cheng-Long Tang - San Jose CA, US
Le Trong Nguyen - Monte Sereno CA, US
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
G06F013/14
G06F013/36
US Classification:
712 29, 710243
Abstract:
A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

High-Performance, Superscalar-Based Computer System With Out-Of-Order Instruction Execution

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US Patent:
6959375, Oct 25, 2005
Filed:
Oct 29, 2002
Appl. No.:
10/282045
Inventors:
Le Trong Nguyen - Monte Sereno CA, US
Derek J. Lentz - Los Gatos CA, US
Yoshiyuki Miyayama - Santa Clara CA, US
Sanjiv Garg - Freemont CA, US
Yasuaki Hagiwara - Santa Clara CA, US
Johannes Wang - Redwood City CA, US
Te-Li Lau - Palo Alto CA, US
Quang H. Trang - San Jose CA, US
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
G06F009/38
G06F009/50
G06F015/16
US Classification:
712 23, 712212, 712213, 712214, 712206, 712 41, 711125, 711148
Abstract:
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
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Yasuaki Hagiwara from Newark, CA, age ~61 Get Report