Search

Xiaoyan Shao

from Tempe, AZ
Age ~39
Get Report
Also known as:
N Shao
Connected to:
Aihua H Shao, 59Alice Shao, 73Catherine Shao, 74Chenyu Shao, 82Chunhong Shao, 52Cindy Shao, 39Duan M Shao, 46Feng L ShaoGuozheng Shao, 39Huilun Shao, 38

Xiaoyan Shao Phones & Addresses

  • Tempe, AZ
  • Tarrytown, NY
  • Dallas, TX
  • Norwalk, CT
  • Toledo, OH
  • 177 White Plains Rd APT 67A, Tarrytown, NY 10591

Publications

Us Patents

Structure And Method Of Forming Electrodeposited Contacts

View page
US Patent:
7405154, Jul 29, 2008
Filed:
Mar 24, 2006
Appl. No.:
11/308433
Inventors:
Cyril Cabral, Jr. - Mahopac NY, US
Hariklia Deligianni - Tenafly NJ, US
Randolph F. Knarr - Putnam Valley NY, US
Sandra G. Malhotra - Santa Clara CA, US
Stephen Rossnagel - Pleasantville NY, US
Xiaoyan Shao - Yorktown Heights NY, US
Anna Topol - Wappingers Falls NY, US
Philippe M. Vereecken - Leuven, BE
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/4763
US Classification:
438630, 438626, 438627, 438631, 438675, 257E21476
Abstract:
A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.

Method And Structure Of Integrated Rhodium Contacts With Copper Interconnects

View page
US Patent:
7843067, Nov 30, 2010
Filed:
Mar 24, 2008
Appl. No.:
12/053969
Inventors:
John M. Cotte - New Fairfield CT, US
Balasubramanian Haran - Watervliet NY, US
Christopher C. Parks - Poughkeepsie NY, US
Xiaoyan Shao - Yorktown Heights NY, US
Eva E. Simonyi - Bronx NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 23/48
US Classification:
257762, 257414, 438630
Abstract:
The present disclosure relates to a microelectronic structure and the manufacture of the microelectronic structure. Specifically, the disclosure relates to an interconnect barrier layer between a rhodium contact structure and a copper interconnect structure in a microelectronic structure. The microelectronic structure provides for low resistance in microelectronic devices.

Method Of Forming Electrodeposited Contacts

View page
US Patent:
7851357, Dec 14, 2010
Filed:
May 30, 2008
Appl. No.:
12/130381
Inventors:
Cyril Cabral, Jr. - Mahopac NY, US
Lili Deligianni - Tenafly NJ, US
Randolph F. Knarr - Yorktown Heights NY, US
Sandra G. Malhotra - Beacon NY, US
Stephen Rossnagel - Pleasantville NY, US
Xiaoyan Shao - Yorktown Heights NY, US
Anna Topol - Yorktown Heights NY, US
Philippe M. Vereecken - Leuven, BE
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/4763
US Classification:
438637, 438643, 438672, 257E21577, 257E21578
Abstract:
A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.

Gate Stack Engineering By Electrochemical Processing Utilizing Through-Gate-Dielectric Current Flow

View page
US Patent:
7868410, Jan 11, 2011
Filed:
Feb 29, 2008
Appl. No.:
12/040350
Inventors:
Philippe M. Vereecken - Leuven, BE
Veeraraghavan S. Basker - Yorktown Heights NY, US
Cyril Cabral, Jr. - Mahopac NY, US
Emanuel I. Cooper - Scarsdale NY, US
Hariklia Deligianni - Tenafly NJ, US
Martin M. Frank - New York NY, US
Rajarao Jammy - Hopewell Junction NY, US
Vamsi Krishna Paruchuri - New York NY, US
Katherine L. Saenger - Ossining NY, US
Xiaoyan Shao - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/70
US Classification:
257499, 438585
Abstract:
A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

Methods Of Fabricating Solar Cell Chips

View page
US Patent:
7897434, Mar 1, 2011
Filed:
Aug 12, 2008
Appl. No.:
12/189911
Inventors:
Hans-Juergen Eickelmann - Nieder-Hilbersheim, DE
Michael Haag - Rodenbach, DE
Harold J. Hovel - Katonah NY, US
Rainer Klaus Krause - Main-Kostheim, DE
Markus Schmidt - Seibersbach, DE
Xiaoyan Shao - Yorktown Heights NY, US
Steven Erik Steen - Peekskill NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/00
US Classification:
438110, 438113, 438636, 257758
Abstract:
A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips.

Method Of Electrodepositing Germanium Compound Materials On A Substrate

View page
US Patent:
7918984, Apr 5, 2011
Filed:
Sep 17, 2007
Appl. No.:
11/856335
Inventors:
Qiang Huang - Ossining NY, US
Andrew J. Kellock - Sunnyvale CA, US
Xiaoyan Shao - Yorktown Heights NY, US
Venkatram Venkatasamy - Edina MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
C25D 5/02
US Classification:
205118, 205123, 205157
Abstract:
A method of electrodepositing germanium compound materials on an exposed region of a substrate structure, which includes forming a plating solution by dissolving at least one germanium salt and at least one salt containing an element other than germanium in water; obtaining a substrate with a clean surface; immersing the substrate in the solution; and electroplating germanium compound materials on the substrate by applying an electrical potential between the substrate and an anode in the plating solution, in which the substrate is included in a semiconductor or phase change device.

Gate Stack Engineering By Electrochemical Processing Utilizing Through-Gate-Dielectric Current Flow

View page
US Patent:
7368045, May 6, 2008
Filed:
Jan 27, 2005
Appl. No.:
11/050790
Inventors:
Philippe M. Vereecken - Sleepy Hollow NY, US
Veeraraghavan S. Basker - Yorktown Heights NY, US
Cyril Cabral, Jr. - Mahopac NY, US
Emanuel I. Cooper - Scarsdale NY, US
Hariklia Deligianni - Tenafly NJ, US
Martin M. Frank - New York NY, US
Rajarao Jammy - Hopewell Junction NY, US
Vamsi Krishna Paruchuri - New York NY, US
Katherine L. Saenger - Ossining NY, US
Xiaoyan Shao - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
C25D 5/02
C25D 11/04
US Classification:
205118, 205324
Abstract:
A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

Phase Change Memory Device With Plated Phase Change Material

View page
US Patent:
8030130, Oct 4, 2011
Filed:
Aug 14, 2009
Appl. No.:
12/541595
Inventors:
Matthew J. Breitwisch - Yorktown Heights NY, US
Eric A. Joseph - White Plains NY, US
Alejandro G. Schrott - New York NY, US
Xiaoyan Shao - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/06
US Classification:
438103, 257E21645
Abstract:
A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell.
Control profile
Xiaoyan Shao from Tempe, AZ, age ~39 Get Report