Resumes
Resumes
Wipawan Yindeepol Phones & Addresses
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318 Apple Blossom Ln, Campbell, CA 95008 (408) 871-2787
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Cupertino, CA
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San Jose, CA
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Fremont, CA
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Corvallis, OR
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Santa Clara, CA
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318 Apple Blossom Ln, Campbell, CA 95008 (408) 921-2787
Work
Position:
Professional/Technical
Education
Degree:
Graduate or professional degree
Emails
Publications
Us Patents
Elimination Of Walkout In High Voltage Trench Isolated Devices
View pageUS Patent:
6362064, Mar 26, 2002
Filed:
Apr 21, 1998
Appl. No.:
09/063074
Inventors:
Joel M. McGregor - Los Altos CA
Rashid Bashir - Mountain View CA
Wipawan Yindeepol - San Jose CA
Rashid Bashir - Mountain View CA
Wipawan Yindeepol - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21331
US Classification:
438318, 257487, 257496, 257565
Abstract:
Walkout in high voltage trench isolated semiconductor devices is inhibited by applying a voltage bias signal directly to epitaxial silicon surrounding the device. Voltage applied to the surrounding epitaxial silicon elevates the initial breakdown voltage of the device and eliminates walkout. This is because voltage applied to the surrounding epitaxial silicon reduces the strength of the electric field between the silicon of the device and the surrounding silicon. Specifically, application of a positive voltage bias signal to surrounding epitaxial silicon equal to or more positive than the most positive potential occurring at the collector during normal operation of the device ensures that no walkout will occur.
Trim Zener Using Double Poly Process
View pageUS Patent:
6979879, Dec 27, 2005
Filed:
Apr 30, 2004
Appl. No.:
10/835698
Inventors:
Wipawan Yindeepol - Campbell CA, US
Andy Strachan - Sunnyvale CA, US
Andy Strachan - Sunnyvale CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L029/00
US Classification:
257530, 257529, 257542
Abstract:
In a zener zap diode device and a system for making such a device using a double poly process, p+ and n+regions are formed in a tub by means of p-doped and n-doped polysilicon regions, and a p-n junction is formed between the p+ region and an n-tub or between the n+ region and a p-tub. Cobalt or other refractory metal is reacted with silicon to form a silicide on at least the p-doped polysilicon region. By reverse biasing the p-n junction and establishing a sufficiently high zap current, the silicide can be forced to migrate across the junction to form a silicide bridge thereby selectively shorting out the p-n junction.
Method Of Forming An Integrated Circuit Including Filling And Planarizing A Trench Having An Oxygen Barrier Layer
View pageUS Patent:
59111097, Jun 8, 1999
Filed:
Feb 13, 1997
Appl. No.:
8/800012
Inventors:
Reda R. Razouk - Sunnyvale CA
Kulwant S. Egan - San Jose CA
Wipawan Yindeepol - San Jose CA
Waclaw C. Koscielniak - Santa Clara CA
Kulwant S. Egan - San Jose CA
Wipawan Yindeepol - San Jose CA
Waclaw C. Koscielniak - Santa Clara CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2162
US Classification:
438424
Abstract:
A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.
Semiconductor Device Trench Isolation Structure With Polysilicon Bias Voltage Contact
View pageUS Patent:
61211486, Sep 19, 2000
Filed:
Jan 26, 1999
Appl. No.:
9/236978
Inventors:
Rashid Bashir - Santa Clara CA
Wipawan Yindeepol - San Jose CA
Wipawan Yindeepol - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21302
US Classification:
438692
Abstract:
A semiconductor device, polysilicon-contacted trench isolation structure that provides improved electrical isolation stability, a method of operating a polysilicon-contacted trench isolated semiconductor device, and a process for manufacturing a polysilicon-contacted trench isolation structure. The trench isolation structure includes an isolation trench formed in a semiconductor substrate. The isolation trench has a layer of trench lining oxide, a layer of trench lining silicon nitride and a trench fill polysilicon (poly 1) layer. Exposed lateral surfaces of the poly 1, which extend above the trench lining silicon nitride, are contacted to another layer of polysilicon (poly 2). The method of operation includes applying a bias voltage to the trench fill poly 1 layer via poly 2. The process for manufacture includes etching an isolation trench that extends through a layer of field oxide and into a semiconductor substrate. After forming layers of trench lining oxide, trench lining silicon nitride and trench fill poly 1 in the isolation trench, the trench lining silicon nitride is etched back to expose lateral surfaces of the trench fill poly 1.
Method Of Forming And Planarizing Deep Isolation Trenches In A Silicon-On-Insulator (Soi) Structure
View pageUS Patent:
58113150, Sep 22, 1998
Filed:
Mar 13, 1997
Appl. No.:
8/816408
Inventors:
Wipawan Yindeepol - San Jose CA
Joel McGregor - Los Altos CA
Rashid Bashir - Santa Clara CA
Kevin Brown - Sunnyvale CA
Joseph Anthony DeSantis - San Jose CA
Joel McGregor - Los Altos CA
Rashid Bashir - Santa Clara CA
Kevin Brown - Sunnyvale CA
Joseph Anthony DeSantis - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2176
US Classification:
437 62
Abstract:
A method of forming and planarizing a deep isolation trench in a silicon-on-insulator (SOI) structure begins with a base semiconductor substrate, a buried insulator layer formed on the base semiconductor substrate, and an active silicon layer formed on the buried insulator layer. First, an ONO layer is formed on the active silicon layer. The ONO layer includes a layer of field oxide, a first layer of silicon nitride and a layer of deposited hardmask oxide. A trench having sidewalls that extend to the buried oxide layer is formed. A layer of trench lining oxide is then formed on the exposed sidewalls of the trench. Then, a second layer of silicon nitride is conformally formed on the substrate. The second nitride layer is then anisotropically etched to remove the nitride from the exposed horizontal surface of the hardmask oxide and the buried oxide in the bottom of the trench, but leaving silicon nitride on the vertical sidewall portions of the hardmask oxide, on the sidewalls of the first nitride layer on the sidewalls of the field oxide and on the trench lining oxide. A layer of polysilicon is then deposited to fill the trench and etched back such that the top surface of the polysilicon substantially corresponds to the top surface of the layer of field oxide.
Integrated Circuit With Trenches And An Oxygen Barrier Layer
View pageUS Patent:
55811108, Dec 3, 1996
Filed:
Aug 17, 1995
Appl. No.:
8/516114
Inventors:
Reda R. Razouk - Sunnyvale CA
Kulwant S. Egan - San Jose CA
Wipawan Yindeepol - San Jose CA
Waclaw C. Koscielniak - Santa Clara CA
Kulwant S. Egan - San Jose CA
Wipawan Yindeepol - San Jose CA
Waclaw C. Koscielniak - Santa Clara CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2712
US Classification:
257513
Abstract:
A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.
Semiconductor Device Trench Isolation Structure With Polysilicon Bias Voltage Contact
View pageUS Patent:
59145234, Jun 22, 1999
Filed:
Feb 17, 1998
Appl. No.:
9/024329
Inventors:
Rashid Bashir - Santa Clara CA
Wipawan Yindeepol - San Jose CA
Wipawan Yindeepol - San Jose CA
Assignee:
National Semiconductor Corp. - Santa Clara CA
International Classification:
H01L 2358
US Classification:
257520
Abstract:
A semiconductor device, polysilicon-contacted trench isolation- structure that provides improved electrical isolation stability, a method of operating a polysilicon-contacted trench isolated semiconductor device, and a process for manufacturing a polysilicon-contacted trench isolation structure. The trench isolation structure includes an isolation trench formed in a semiconductor substrate. The isolation trench has a layer of trench lining oxide, a layer of trench lining silicon nitride and a trench fill polysilicon (poly 1) layer. Exposed lateral surfaces of the poly 1, which extend above the trench lining silicon nitride, are contacted to another layer of polysilicon (poly 2). The method of operation includes applying a bias voltage to the trench fill poly 1 layer via poly 2. The process for manufacture includes etching an isolation trench that extends through a layer of field oxide and into a semiconductor substrate. After forming layers of trench lining oxide, trench lining silicon nitride and trench fill poly 1 in the isolation trench, the trench lining silicon nitride is etched back to expose lateral surfaces of the trench fill poly 1.