US Patent:
20090160475, Jun 25, 2009
Inventors:
Anwar Ali - San Jose CA, US
Thinh Tran - San Jose CA, US
Wilson Choi - San Jose CA, US
International Classification:
G01R 31/26
G06F 17/50
Abstract:
An apparatus and method for reducing the number of package pins in a chip package which must be budgeted for test purposes. In one embodiment, the invention achieves this by housing test balls in the depopulated center of a package ball array. The test balls are used to test a chip package prior to connection with a printed wiring board (PWB)/printed circuit board (PCB). After tests are completed, and when the chip package is connected to a PWB/PCB, the test balls may be left electrically isolated and unconnected. In another embodiment, the test balls are located in previously unused interstitial sites in a package ball array.
