William A Nesheim

6401174, Jun 4, 2002

Sep 4, 1998

09/148734

Erik E. Hagersten - Palo Alto CA
Christopher J. Jackson - Westford MA
Aleksandr Guzovskiy - Lowell MA
William A. Nesheim - Windham NH

Sun Microsystems, Inc. - Palo Alto CA

G06F 1200

711147, 156168

In one embodiment, a multiprocessing computer system includes a plurality of nodes. The plurality of nodes may be interconnected through a global interconnect network which supports cluster communications. An initiating node may launch a request to a remote nodes memory. In the event of an error, an error status register of a system interface of the launching cluster node is set to indicate the occurrence of an error. The error may be the result of an access violation, or the result of a time-out occurrence in either the remote node or the initiating node. Various other errors may alternatively be reported. The system interface advantageously includes a plurality of error status registers, with a separate error status register provided for each processor included in the node. A process running on any of the processors of the node reads an error by issuing a transaction to a unique address, wherein the unique address is independent of the processor upon which the process is running. The unique address as well as the transaction ID indicative of the processor which is attempting to read an error status are used by the system interface to determine which of the plurality of error status registers to access.

6449700, Sep 10, 2002

Sep 4, 1998

09/148735

Erik E. Hagersten - Palo Alto CA
Christopher J. Jackson - Westford MA
Aleksandr Guzovskiy - Lowell MA
William A. Nesheim - Windham NH

Sun Microsystems, Inc. - Palo Alto CA

G06F 1200

711152, 711153, 711170

A multiprocessing system includes a plurality of nodes interconnected through a global interconnect network which supports cluster communications. An initiating node may launch a request to a remote nodes memory. A cluster protection mechanism is employed within a system interface of the remote node. The system interface, which is coupled between the global interconnect network and a local bus of the remote node, includes a memory management unit, referred to as a cluster MMU, including a plurality of entries which are selectable on a page basis. Depending upon the particular address of a received global transaction, an entry within the memory management unit is retrieved. The entry includes various fields which may be used to protect against accesses by unauthorized nodes, and to specify the local physical address to be conveyed upon the local bus. A field of the entry is further provided to control the type of operation performed upon the local bus by the system interface in response to the global interface. In one implementation, several different command types may be specified by the particular entry of the memory management unit, including normal memory operations, atomic test and set operations, I/O operations and interrupt operations, among others.

59580194, Sep 28, 1999

Jul 1, 1996

8/674328

Erik E. Hagersten - Palo ALto CA
Robert C. Zak - Lexington MA
Shaw-Wen Yang - Concord MA
Aleksandr Guzovskiy - Lowell MA
William A. Nesheim - Windham NH
Monica C. Wong-Chan - Concord MA
Hien Nguyen - Newton MA

Sun Microsystems, Inc. - Palo Alto CA

G06F 1342

709400

When a processor within a computer system performs a synchronization operation, the system interface within the node delays subsequent transactions from the processor until outstanding coherency activity is completed. Therefore, the computer system may employ asynchronous operations. The synchronization operations may be used when needed to guarantee global completion of one or more prior asynchronous operations. In one embodiment, the synchronization operation is placed into a queue within the system interface. When the synchronization operation reaches the head of the queue, it may be initiated within the system interface. The system interface further includes a request agent comprising multiple control units, each of which may concurrently service coherency activity with respect to a different transaction. Furthermore, the system interface includes a synchronization control vector register which stores a bit for each control unit. Upon initiation of the synchronization operation within the system interface, bits corresponding to those control units which are performing coherency activity (i. e.

52222160, Jun 22, 1993

Jul 12, 1991

7/729429

Edward C. Parish - Brookline MA
Robert A. Doolittle - Acton MA
Sharon E. Gillett - Watertown MA
Thomas J. Moser - Somerville MA
William A. Nesheim - Windham NH
David L. Satterfield - Everett MA
James P. Tardiff - Framingham MA

Thinking Machines Corporation - Cambridge MA

G06F 1300

395275

A high performance communications interface device for connecting a high speed computer to a high performance communications bus. The high performance communications interface device includes a high performance communications interface device processor, a source interface, a destination interface and at least one I/O processor which controls the transfer of data to the high speed computer from the high performance communications bus and from the high speed computer to the high performance communications bus.

58623167, Jan 19, 1999

Jul 1, 1996

8/674276

Erik E. Hagersten - Palo Alto CA
John R. Catenzaro - Londonderry NH
William A. Nesheim - Windham NH
Monica C. Wong-Chan - Concord MA
Robert C. Zak - Lexington MA
Paul N. Loewenstein - Palo Alto CA

Sun Microsystems, Inc. - Mountainview CA

G06F 1100

39518213

Protocol agents involved in the performance of global coherency activity detect errors with respect to the activity being performed. The errors are logged by a computer system such that diagnostic software may be executed to determine the error detected and to trace the error to the erring software or hardware. In particular, information regarding the first error to be detected is logged. Subsequent errors may receive more or less logging depending upon programmable configuration values. Additionally, those errors which receive full logging may be programmably selected via error masks. The protocol agents each comprise multiple independent state machines which independently process requests. If the request which a particular state machine is processing results in an error, the particular state machine may enter a freeze state. Information regarding the request which is collected by the state machine may thereby be saved for later access.

58976647, Apr 27, 1999

Jul 1, 1996

8/673043

William A. Nesheim - Windham NH
Aleksandr Guzovskiy - Lowell MA

Sun Microsystems, Inc. - Palo Alto CA

G06F 1210

711206

In a multiprocessor computing system, virtual memory addresses are mapped to local physical memory addresses of an attraction memory, containing a replication of the data contained at remote physical addresses, in a node of the system. A mapping table is created and maintained in each node of the system to supplement a conventional page table. The mapping table is used to map a global physical address to a local physical address of the replicated page of memory. System performance is enhanced by subsequent access to the data stored at the local physical address, as opposed to the remote physical address.

58988408, Apr 27, 1999

Jul 1, 1996

8/673049

Aleksandr Guzovskiy - Lowell MA
William A. Nesheim - Windham NH
Ashok Singhal - Redwood City CA

Sun Microsystems, Inc. - Palo Alto CA

G06F 1516

39520056

In a multiprocessor system, a method, apparatus, and article of manufacture for maintaining the proper sequence of store/write operations between multiple processors to remote I/O devices without requiring changes to application software. A synchronizer is employed to synchronize write operations to the remote I/O device, and the write operations are synchronized individually upon detection and emulation, or as a group upon detection of the release of a mutual exclusion lock.