Werner A Rausch

6337253, Jan 8, 2002

Nov 7, 2000

09/707305

Bijan Davari - Mahopac NY
Effendi Leobandung - Wappingers Falls NY
Werner Rausch - Stormville NY
Ghavam G. Shahidi - Elmsford NY

International Business Machines Corporation - Armonk NY

H01L 2120

438393, 438155, 438241

A process for making a capacitor for a silicon-on-insulator (SOI) structure. The SOI structure has a p-type silicon base layer, a buried oxide layer, a silicon layer, and an n layer formed within a portion of the p-type silicon base layer. The process comprises the steps of forming a buried oxide layer and a silicon layer in the p-type silicon base layer, forming an n layer in a portion of the p-type silicon base layer, and forming electrically conductive paths to the p-type silicon base layer and the n layer extending through the buried oxide and silicon layers.

6429482, Aug 6, 2002

Jun 8, 2000

09/589719

James A. Culp - Poughkeepsie NY
Jawahar P. Nayak - Wappingers Falls NY
Werner A. Rausch - Stormville NY
Melanie J. Sherony - Wappingers Falls NY
Steven H. Voldman - South Burlington VT
Noah D. Zamdmer - Sleepy Hollow NY

International Business Machines Corporation - Armonk NY

H01L 2976

257345, 257335, 257339

A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

6432777, Aug 13, 2002

Jun 6, 2001

09/875842

Werner Rausch - Stormville NY
Ralph W. Young - Poughkeepsie NY

International Business Machines Corporation - Armonk NY

H01L 2184

438275, 438151, 438149

A method of manufacturing a metal oxide semiconductor field effect transistor (MOSFET). The method forms an insulator layer over a substrate and a doped layer over the insulator layer. Further, the invention patterns a conductor layer over the doped layer. The conductor layer includes gate conductors. The invention implants a second impurity through the conductor layer and into the doped layer. The second impurity is of an opposite type than that of the first type of impurity. Also, the second impurity decreases the effective concentration of the first impurity in the doped layer. The amount of the second type of impurity that penetrates through the conductor layer into the doped layer changes depending upon the length of the gate conductors within the conductor layer.

6521947, Feb 18, 2003

Jan 28, 1999

09/239327

Atul Ajmera - Wappingers Falls NY
Effendi Leobandung - Wappingers Falls NY
Werner Rausch - Stormville NY
Dominic J. Schepis - Wappingers Falls NY
Ghavam G. Shahidi - Elmsford NY

International Business Machines Corporation - Armonk NY

H01L 2701

257347, 257508

A method for forming a substrate contact in a substrate that includes a silicon on insulator region. A shallow isolation trench is formed in the silicon on insulator substrate. The shallow isolation trench is filled. Photoresist is deposited on the substrate. A contact trench is formed in the substrate through the filled shallow isolation trench, silicon on insulator, and silicon substrate underlying the silicon on insulator region. The contact trench is filled, wherein the material filling the contact trench forms a contact to the silicon substrate.

6624459, Sep 23, 2003

Apr 12, 2000

09/547893

William R. Dachtera - Poughkeepsie NY
Rajiv V. Joshi - Yorktown Heights NY
Werner A. Rausch - Stormville NY

International Business Machines Corp. - Armonk NY

H01L 2972

257296, 257347, 257350, 257369

Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetrate to the underlying insulator layer, resulting in a FET in the surface of an SOI layer with a body or substrate contact formed at a shared contact. FETs are formed on SOI silicon islands located on a BOX layer and isolated by shallow trench isolation (STI). NFET islands in the SRAM cells include a body contact to a P-type diffusion in the NFET island. Each NFET in the SRAM cells include at least one shallow source/drain diffusion that is shallower than the island thickness. A path remains under the shallow diffusions between NFET channels and the body contact. The P-type body contact diffusion is a deep diffusion, the full thickness of the island.

6686629, Feb 3, 2004

Aug 18, 1999

09/377331

Fariborz Assaderaghi - Mahopac NY
Werner Rausch - Stormville NY
Dominic Joseph Schepis - Wappingers Falls NY
Ghavam G. Shahidi - Elmsford NY

International Business Machines Corporation - Armonk NY

H01L 2976

257347, 254344, 254347, 254348, 254345, 254350, 254359

Disadvantages of the floating body of a SOI MOSFET are addressed by providing a pocket halo implant of indium beneath the gate and in the channel region of the semiconductor SOI layer of the MOSFET. Also provided is the method for fabricating the device.

6713791, Mar 30, 2004

Jan 26, 2001

09/770788

Louis L. Hsu - Fishkill NY
Rajiv V. Joshi - Yorktown Heights NY
Fariborz Assaderaghi - Mahopac NY
Dan Moy - Bethel CT
Werner Rausch - Stormville NY
James Culp - Poughkeepsie NY

IBM Corporation - Armonk NY

H01L 2974

257200, 257133, 257147, 257162

A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc.

6750109, Jun 15, 2004

Jul 1, 2002

10/064305

James A. Culp - Poughkeepsie NY
Jawahar P. Nayak - Wappingers Falls NY
Werner A. Rausch - Stormville NY
Melanie J. Sherony - Wappingers Falls NY
Steven H. Voldman - South Burlington VT
Noah D. Zamdmer - Sleepy Hollow NY

International Business Machines Corporation - Armonk NY

H01L 21331

438354, 438204, 438234

A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.