Resumes
Resumes
Wayne Westgate Phones & Addresses
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1181 Sesame Dr, Sunnyvale, CA 94087 (408) 245-9098
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Middleburg, FL
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1181 Sesame Dr, Sunnyvale, CA 94087
Publications
Us Patents
Quad-Ridge Waveguide Mixer
View pageUS Patent:
46913807, Sep 1, 1987
Filed:
May 5, 1986
Appl. No.:
6/859617
Inventors:
Wayne F. Westgate - Sunnyvale CA
Assignee:
Avantek, Inc. - Santa Clara CA
International Classification:
H04B 126
US Classification:
455328
Abstract:
A double-balanced waveguide mixer is disclosed that utilizes a quad-ridge waveguide and a quad-diode ring. In a down-converter version of the mixer, the input signal is applied to one pair of opposed ridges of the quad-ridge waveguide and the local oscillator signal is applied to the other pair of opposed ridges. The diode ring is coupled through capacitors to one pair of opposed ridges, and is directly connected to the other pair of opposed ridges. The intermediate frequency is tapped off at the junction between the capacitors and the diode ring.
Clock Circuit For Generating A High Resolution Output From A Low Resolution Clock
View pageUS Patent:
59031760, May 11, 1999
Filed:
Sep 4, 1996
Appl. No.:
8/707435
Inventors:
Wayne F. Westgate - Sunnyvale CA
Assignee:
Litton Systems, Inc. - Woodland Hills CA
International Classification:
H03K3/00
US Classification:
327295
Abstract:
A high resolution clock circuit apparatus and a method of generating a high resolution clock output from a lower resolution clock input utilizes conventional technology. A standard clock generates a clock frequency which is divided by a flip-flop circuit and is applied to a low skew differential clock driver which distributes the clock into a plurality of separate outputs, each output is applied to a different length delay line. The output of each delay line is applied to a latching circuit, such as a low power octal ECL/TTL bidirectional translator. Each of the plurality of delay lines is sampled and a time word is latched when a time measurement is to be made. In this event, a control signal toggles from low to high which latches a digital word representing that subnanosecond interval of time. A shift register also receives the input clock frequency and includes a feedback loop and is applied to the latch circuit. The output of the two latches are input into a PROM used to convert the input code into a binary coded decimal.