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Walter R Merry

from Sunnyvale, CA
Age ~61
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Also known as:
Walter Merry Richardson
Phone and address:
982 Iowa Ave, Sunnyvale, CA 94086
Related to:
Donna M Dowd, 56Virginia M Merry, 94Daniel J Devine, 59Daniel J Devine, 40Virginia W MerryPatsy Wright, 67
Connected to:
Alicia Merry, 61Allison A Merry, 36Andrea E Merry, 56Betsy Merry, 72Betty M Merry, 83Bobby D Merry, 72Cassie C Merry, 54Cecilia C Merry, 61Claire Merry, 54Claude R Merry, 89

Walter Merry Phones & Addresses

  • 982 Iowa Ave, Sunnyvale, CA 94086
  • Santa Clara, CA
  • Cupertino, CA
  • Berkeley, CA

Work

Company: Comet plasma control technologies Jan 2014 Position: Engineer, rf systems

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of California, Berkeley Specialities: Philosophy, Chemistry

Skills

Design of Experiments • Semiconductors • Rie • Thin Films • Plasma Processing • Rf Engineering • Rf Networks • Surface Analysis • Mathcad • Uhv

Industries

Semiconductors

Resumes

Resumes

Walter Merry Photo 1

Engineer, Rf Systems

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Comet Plasma Control Technologies
Engineer, Rf Systems
Applied Materials 2005 - 2013
Product Development Engineer
Applied Materials 2001 - 2005
Technology Development Engineer
Applied Materials 1997 - 2001
Member of Technical Staff, Process Engineer
Education:
University of California, Berkeley
Doctorates, Doctor of Philosophy, Philosophy, Chemistry University of Pennsylvania
Bachelors, Bachelor of Arts, Chemistry
Skills:
Design of Experiments
Semiconductors
Rie
Thin Films
Plasma Processing
Rf Engineering
Rf Networks
Surface Analysis
Mathcad
Uhv

Publications

Us Patents

Oxide Plasma Etching Process With A Controlled Wineglass Shape

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US Patent:
6355557, Mar 12, 2002
Filed:
Jul 22, 1998
Appl. No.:
09/121190
Inventors:
James A. Stinnett - Mountain View CA
Cynthia B. Brooks - Sunnyvale CA
Walter R. Merry - Cupertino CA
Jason Regis - Amesbury MA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 214763
US Classification:
438640, 438689, 438700, 438712, 438711, 438713
Abstract:
An oxide etching method, particularly applicable to forming through an oxide layer a wineglass shaped contact or via hole of controlled shape. The wineglass hole is particularly useful for eased metal hole filling. The bowl is etched by first etching an anisotropic hole through a mask aperture, and then isotropically etching through the same mask aperture. The relative periods of the anisotropic and isotropic etch determine the lateral-to-vertical dimensions of the bowl. The stem is then etched through the same mask aperture with a strongly anisotropic etch. The isotropic etch may be performed in the same chamber as the anisotropic etch or may advantageously be performed in a separate etch chamber having a remote plasma source.

Semiconductor Fabrication Process

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US Patent:
6432830, Aug 13, 2002
Filed:
May 15, 1998
Appl. No.:
09/079845
Inventors:
Walter Richardson Merry - Cupertino CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21302
US Classification:
438706, 438712, 438719, 438723, 438743
Abstract:
Process for treating a semiconductor substrate polymeric etchant deposits silicon lattice damage and native silicon dioxide layers are removed in sequential process steps. The polymeric etchant deposits are removed using an activated cleaning gas comprising inorganic fluorinated gas and an oxygen gas. Silicon lattice damage are etched using an activated etching gas. Thereafter, an activated reducing gas comprising a hydrogen-containing gas is used to reduce the native silicon dioxide layer on the substrate to a silicon layer. Subsequently, a metal layer is deposited on the substrate and the substrate annealed to form a metal silicide layer Removal of the polymeric etchant deposits the silicon lattice damage and the native silicon oxide layer increases the interfacial conductivity of the metal silicide layer to the underlying silicon-containing substrate.

Method For Plasma Etching A Dielectric Layer

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US Patent:
7056830, Jun 6, 2006
Filed:
Sep 3, 2003
Appl. No.:
10/655231
Inventors:
Walter R. Merry - Sunnyvale CA, US
Cecilia Y. Mak - Union City CA, US
Kam S. Law - Union City CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/302
US Classification:
438700, 438706, 438723
Abstract:
A method of etching a dielectric layer formed on a substrate including a sequence of processing cycles, wherein each cycle comprises steps of depositing an inactive polymeric film, activating the film to etch the structure, and removing the film is disclosed. In one embodiment, the method uses a fluorocarbon gas to form the polymeric film and a substrate bias to activate such film.

Method And Apparatus For In-Situ Film Stack Processing

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US Patent:
7358192, Apr 15, 2008
Filed:
Apr 8, 2004
Appl. No.:
10/821723
Inventors:
Walter R. Merry - Sunnyvale CA, US
Quanyuan Shang - Saratoga CA, US
John M. White - Hayward CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/02
US Classification:
438706, 438710, 216 58, 216 41, 216 67, 216 74, 216 75, 216 79, 15634535, 15634531
Abstract:
Embodiments of a cluster tool, processing chamber and method for processing a film stack are provided. In one embodiment, a method for in-situ etching of silicon and metal layers of a film stack is provided that includes the steps of etching an upper metal layer of the film stack in a processing chamber to expose a portion of an underlying silicon layer, and etching a trench in the silicon layer without removing the substrate from the processing chamber. The invention is particularly useful for thin film transistor fabrication for flat panel displays.

Matching Network Characterization Using Variable Impedance Analysis

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US Patent:
7554334, Jun 30, 2009
Filed:
Sep 28, 2006
Appl. No.:
11/536197
Inventors:
Steven C. Shannon - San Mateo CA, US
Daniel J. Hoffman - Saratoga CA, US
Steven Lane - San Jose CA, US
Walter R. Merry - Sunnyvale CA, US
Jivko Dinev - Cupertino CA, US
Assignee:
Applied Marterials, Inc. - Santa Clara CA
International Classification:
G01R 31/02
US Classification:
324535, 324600, 333 32
Abstract:
Embodiments of a method of calculating the equivalent series resistance of a matching network using variable impedance analysis and matching networks analyzed using the same are provided herein. In one embodiment, a method of calculating the equivalent series resistance of a matching network includes the steps of connecting the matching network to a load; measuring an output of the matching network over a range of load impedances; and calculating the equivalent series resistance of the matching network based upon a relationship between the measured output and the load resistance. The load may be a surrogate load or may be a plasma formed in a process chamber.

Apparatus And Method For Front Side Protection During Backside Cleaning

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US Patent:
7879183, Feb 1, 2011
Filed:
Feb 27, 2008
Appl. No.:
12/038499
Inventors:
Imad Yousif - San Jose CA, US
Ying Rui - Santa Clara CA, US
Nancy Fung - Livermore CA, US
Martin Jeffrey Salinas - San Jose CA, US
Ajit Balakrishna - Sunnyvale CA, US
Anchel Sheyner - San Francisco CA, US
Shahid Rauf - Pleasanton CA, US
Walter R. Merry - Sunnyvale CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/306
C23C 16/00
C23C 16/455
US Classification:
15634534, 15634533, 118715
Abstract:
Embodiments of the present invention provide apparatus and method for front side protection while processing side and backside of a substrate. One embodiment of the present invention provides a showerhead configured to provide a purge gas to a front side of a substrate during a backside etch processing. The showerhead comprises a body configured to be disposed over the front side of the substrate. The body has a process surface configured to face the front side of the substrate. The process surface has an outer circular region, a central region, a middle region between the outer central region and the central region. The first plurality of holes are distributed in the outer circular region and configured to direct the purge gas towards an edge area of the front side of the substrate. No gas delivery hole is distributed within a substantial portion of the middle region.

Improving Plasma Process Uniformity Across A Wafer By Apportioning Power Among Plural Vhf Sources

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US Patent:
7879731, Feb 1, 2011
Filed:
Apr 11, 2007
Appl. No.:
11/733764
Inventors:
Kenneth S. Collins - San Jose CA, US
Hiroji Hanawa - Sunnyvale CA, US
Kartik Ramaswamy - San Jose CA, US
Shahid Rauf - Pleasanton CA, US
Kallol Bera - San Jose CA, US
Lawrence Wong - Fremont CA, US
Walter R. Merry - Sunnyvale CA, US
Matthew L. Miller - Fremont CA, US
Steven C. Shannon - San Mateo CA, US
Andrew Nguyen - San Jose CA, US
James P. Cruse - Soquel CA, US
James Carducci - Sunnyvale CA, US
Troy S. Detrick - Los Altos CA, US
Subhash Deshmukh - San Jose CA, US
Jennifer Y. Sun - Sunnyvale CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/302
US Classification:
438714, 438 8, 438706, 15634548
Abstract:
A method is provided for processing a workpiece in a plasma reactor chamber having electrodes including at least a ceiling electrode and a workpiece support electrode. The method includes coupling respective RF power sources of respective VHF frequencies f and f to either (a) respective ones of the electrodes or (b) a common one of the electrodes, where f is sufficiently high to produce a center-high non-uniform plasma ion distribution and f is sufficiently low to produce a center-low non-uniform plasma ion distribution. The method further includes adjusting a ratio of an RF parameter at the f frequency to the RF parameter at the f frequency so as to control plasma ion density distribution, the RF parameter being any one of RF power, RF voltage or RF current.

Plasma Process Uniformity Across A Wafer By Apportioning Ground Return Path Impedances Among Plural Vhf Sources

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US Patent:
7884025, Feb 8, 2011
Filed:
Apr 11, 2007
Appl. No.:
11/733767
Inventors:
Kenneth S. Collins - San Jose CA, US
Hiroji Hanawa - Sunnyvale CA, US
Kartik Ramaswamy - San Jose CA, US
Shahid Rauf - Pleasanton CA, US
Kallol Bera - San Jose CA, US
Lawrence Wong - Fremont CA, US
Walter R. Merry - Sunnyvale CA, US
Matthew L. Miller - Fremont CA, US
Steven C. Shannon - San Mateo CA, US
Andrew Nguyen - San Jose CA, US
James P. Cruse - Soquel CA, US
James Carducci - Sunnyvale CA, US
Troy S. Detrick - Los Altos CA, US
Subhash Deshmukh - San Jose CA, US
Jennifer Y. Sun - Sunnyvale CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/302
US Classification:
438714, 438 8, 438706, 438710, 15634548
Abstract:
In a plasma reactor chamber a ceiling electrode and a workpiece support electrode, respective RF power sources of respective VHF frequencies f and f are coupled to either respective ones of the electrodes or to a common one of the electrodes, where f is sufficiently high to produce a center-high non-uniform plasma ion distribution and f is sufficiently low to produce a center-low non-uniform plasma ion distribution. Respective center ground return paths are provided for RF current passing directly between the ceiling electrode and the workpiece support electrode for the frequencies f and f, and an edge ground return path is provided for each of the frequencies f and f. The impedance of at least one of the ground return paths is adjusted so as to control the uniformity of the plasma ion density distribution.

Wikipedia

William Walter Merry

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William Walter Merry (18351918) was an English classical scholar, clergyman, and educator. William Merry was born in Evesham, Worcestershire and was educated at Cheltenham College ...
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Walter R Merry from Sunnyvale, CA, age ~61 Get Report