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Walter F Bridgewater

from Boulder, CO
Deceased
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Also known as:
Walter Francis Bridgewater, Walter M Bridgewater, Walter R
Phone and address:
4669 Anasazi Ct, Boulder, CO 80303
Related to:
Long H Nguyen, 36Lisako F Bridgewater, 42Gary J BridgewaterEliko C Bridgewater, 40Marin R Ripsam, 39Mary B Bridgewater, 72Danielle Bridgewater, 40Miyuki Y Bridgewater, 67Franz Ripsam, 73James K Bridgewater, 34
Connected to:
Alaina M Bridgewater, 43Alicia L Bridgewater, 47Andrea J Bridgewater, 32April A Bridgewater, 55Betty P Bridgewater, 91Bobby A Bridgewater, 48Brandie E Bridgewater, 42Charles R Bridgett, 79Dana L Bridgewater, 41Darren K Bridgett, 60

Walter Bridgewater Phones & Addresses

  • 4669 Anasazi Ct, Boulder, CO 80303
  • 630 Catala Ct, Santa Clara, CA 95050 (408) 615-1439
  • Keaau, HI
  • 8720 Via Media Way, Elk Grove, CA 95624 (916) 685-4583
  • Sacramento, CA
  • Klamath, CA
  • San Jose, CA
  • Walnut, CA
  • Redwood City, CA

Publications

Us Patents

Method And Apparatus For A Programmable Deskew Circuit

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US Patent:
6915462, Jul 5, 2005
Filed:
Jul 30, 2002
Appl. No.:
10/209552
Inventors:
Barry Allen Davis - Union City CA, US
Walter F. Bridgewater - San Jose CA, US
Assignee:
Adaptec, Inc. - Milpitas CA
International Classification:
G11B020/20
US Classification:
714700, 370508
Abstract:
An invention is provided for a deskewer that corrects skew on a data channel. The deskewer includes a delay calculator that calculates deskew data indicating the amount of delay needed to correct skew on a data channel. Coupled to the delay calculator is a deskew circuit that receives the deskew data from the delay calculator and uses the deskew data to delay a bit stream on the data channel.

Methods And Apparatus To Correct Duty Cycle

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US Patent:
6981185, Dec 27, 2005
Filed:
Aug 9, 2002
Appl. No.:
10/215919
Inventors:
Barry Allen Davis - Union City CA, US
Walter F. Bridgewater - San Jose CA, US
Assignee:
Adaptec, Inc. - Milpitas CA
International Classification:
G06F011/00
US Classification:
714707, 714709
Abstract:
An apparatus for correcting duty cycle error is provided which includes circuitry capable of determining existence of a duty cycle error from input data received over data transmissions lines where the circuitry generates duty cycle correction data based on the duty cycle error. The apparatus also includes a digital analog converter (DAC) being coupled to the circuitry where the DAC is capable of receiving a magnitude portion of the duty cycle correction data from the circuitry. The apparatus further includes an adjustable bias driver being coupled to the circuitry, the DAC and the data transmission lines. The adjustable bias driver receives the magnitude portion of the duty cycle correction data from the DAC and receives a polarity portion of the duty cycle correction data from the circuitry where the adjustable bias driver adjusts the polarity of signals applied to the data transmission lines for correcting the duty cycle error.

System And Method For Staging Concurrent Accesses To A Memory Address Location Via A Single Port Using A High Speed Sampling Clock

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US Patent:
7184359, Feb 27, 2007
Filed:
Dec 3, 2004
Appl. No.:
11/003292
Inventors:
Walter F. Bridgewater - San Jose CA, US
Anup Nayak - Fremont CA, US
Dimitris C. Pantelakis - Austin TX, US
S. Babar Raza - San Jose CA, US
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G11C 8/00
US Classification:
365233, 365154, 36523005
Abstract:
A memory device, apparatus and method are provided for accessing memory cells. The device, apparatus, and method allow two or more electronic subsystems with corresponding external ports to access a single array of memory elements via a single internal port. Address, data, and control signals from each of the external ports are multiplexed onto the word line drivers and de-multiplexed from the sense amplifiers. Multiplexing and de-multiplexing operations are sequenced based on a state machine that receives synchronized signals from the external port. The synchronized signal can be clock signals that are synchronized to a high-speed sampling clock. Synchronization and sequencing functions can occur over a relatively few number of cycles of the high-speed sampling clock to minimize the time for resolving access conflicts, thereby maximizing the number of external ports which can access the internal port of the array.

Method And Apparatus For Data Bit Align

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US Patent:
7324421, Jan 29, 2008
Filed:
Aug 13, 2002
Appl. No.:
10/218313
Inventors:
Barry Allen Davis - Union City CA, US
Walter F. Bridgewater - San Jose CA, US
Assignee:
Adaptec, Inc. - Milpitas CA
International Classification:
G11B 11/00
US Classification:
369 5334, 375371
Abstract:
An invention is provided for data bit align. The invention includes a multiplexer that receives a data sample word as data input and also receives a clock sample word as select input. The multiplexer selects a data bit from the data sample word based on the clock sample word. Generally, the multiplexer can select the data bit from the data sample word corresponding to a position of the clock edge in the clock sample word. The invention also includes an output register, which is coupled to the multiplexer. The output register stores the selected data bit from the multiplexer and provides the selected data bit to remaining system components.

Method And Device For Selecting One Of Multiple Clock Signals Based On Frequency Differences Of Such Clock Signals

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US Patent:
7343510, Mar 11, 2008
Filed:
Dec 21, 2004
Appl. No.:
11/019731
Inventors:
Mark Ross - San Carlos CA, US
S. Babar Raza - San Jose CA, US
Dimitris Pantelakis - Austin TX, US
Anup Nayak - Fremont CA, US
Walter Bridgewater - San Jose CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G06F 1/12
US Classification:
713500, 713400, 713502, 713503, 327 1, 327 48, 331 11
Abstract:
A clock detection and selection circuit () can include a first counter (-) that generates a first count value CNT according to a first clock signal CLK and a second counter (-) that generates a second count value CNT according to a second clock signal CLK. First separation-detect logic (-) and second separation-detect logic (-) determine if a pre-specified difference exists between a first count value (CNT/CNT′) and second count value (CNT/CNT′). According to such determinations, separation information (INF and INF) can be generated indicating which clock signal (CLK or CLK) is faster. Selection logic () can select a faster of the clock signals (CLK or CLK) if the separation information values confirm one another.

Data Interface That Is Configurable Into Separate Modes Of Operation For Sub-Bit De-Skewing Of Parallel-Fed Data Signals

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US Patent:
7359407, Apr 15, 2008
Filed:
Aug 27, 2002
Appl. No.:
10/228640
Inventors:
Derwin W. Mattos - San Jose CA, US
Walter F. Bridgewater - San Jose CA, US
Michael H. Herschfelt - Felton CA, US
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H04J 3/06
US Classification:
370509, 370516, 375371, 713375, 713400, 714700
Abstract:
A data interface is provided that can de-skew data signals by taking into account different skewing effects on each data signal. The data interface can be used, for example, in a communication system and can be configured to operate in one of three possible modes of operation. In the first mode, de-skewing is fixed prior to the sample logic. In the second mode, de-skewing is periodically changed automatically as the amount of skew changes based on training signals that are periodically sent into the data interface. The combination of the data phase count and the positive and negative clock width pulse counts will then determine where the final transition or edge of each data signal is to be placed within a bit. The third mode of operation involves an override or programmatic modification of the second mode of operation based on values stored in a register.

Low Voltage Differential Dual Receiver

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US Patent:
20020017920, Feb 14, 2002
Filed:
Sep 26, 2001
Appl. No.:
09/965210
Inventors:
Walter Bridgewater - San Jose CA, US
Assignee:
Adaptec, Inc.
International Classification:
H03K019/0175
US Classification:
326/082000
Abstract:
A low-voltage differential dual receiver for a SCSI bus uses a symmetrical driver by doing without a termination bias voltage. The data phase and protocol phase of SCSI communication are separated by using two receivers and optimizing each receiver for its particular function. A high-speed receiver is used when transmitting data at high-speeds, and a lower performance, low-speed receiver is used for other SCSI phases. A built-in offset allows the low-speed receiver to operate correctly during bus arbitration. The built-in offset in the low-speed receiver takes the place of the termination bias voltage in a traditional SCSI bus and is implemented in a variety of ways. In a first embodiment, an N-well generation circuit produces a bulk voltage for one transistor of the differential transistor pair that is different than a supply voltage supplied to the bulk of the other transistor. In a second embodiment, each of the transistors of the pair is implanted with a different dosage to change the threshold voltage for each. In a third embodiment, resistors of different sizes are attached to the source of each transistor in the pair in order to produce a different voltage at each source. In a fourth embodiment, two replica comparators are used to monitor an offset voltage of the differential receiver and to send control signals to an adjustable current source. The current source is adjusted by having an up-down counter switch on and off various legs of the current source.

Low Voltage Differential Dual Receiver

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US Patent:
6307401, Oct 23, 2001
Filed:
Jan 6, 2000
Appl. No.:
9/479464
Inventors:
Walter Francis Bridgewater - San Jose CA
Assignee:
Adaptec, Inc. - Milpitas CA
International Classification:
H03K 190175
G01R 1900
US Classification:
326 86
Abstract:
A low-voltage differential dual receiver for a SCSI bus uses a symmetrical driver by doing without a termination bias voltage. The data phase and protocol phase of SCSI communication are separated by using two receivers and optimizing each receiver for its particular function. A high-speed receiver is used when transmitting data at high-speeds, and a lower performance, low-speed receiver is used for other SCSI phases. A built-in offset allows the low-speed receiver to operate correctly during bus arbitration. The built-in offset in the low-speed receiver takes the place of the termination bias voltage in a traditional SCSI bus and is implemented in a variety of ways. In a first example, an N-well generation circuit produces a bulk voltage for one transistor of the differential transistor pair that is different than a supply voltage supplied to the bulk of the other transistor. In a second example, each of the transistors of the pair is implanted with a different dosage to change the threshold voltage for each. In a third example, resistors of different sizes are attached to the source of each transistor in the pair in order to produce a different voltage at each source.
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Walter F Bridgewater from Boulder, CODeceased Get Report