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Vladislav Y Potanin

from Granite Bay, CA
Age ~64

Vladislav Potanin Phones & Addresses

  • 4731 Copperfield Cir, Granite Bay, CA 95746
  • Truckee, CA
  • Mountain View, CA
  • 7270 Ventana Dr, San Jose, CA 95129 (408) 996-7179
  • Los Angeles, CA
  • Campbell, CA
  • Cupertino, CA
  • 7270 Ventana Pl, San Jose, CA 95129 (619) 691-0254

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Business Records

Name / Title
Company / Classification
Phones & Addresses
Vladislav Y. Potanin
President
Socblox
Business Services at Non-Commercial Site · Nonclassifiable Establishments
7270 Ventana Pl, San Jose, CA 95129

Publications

Us Patents

Charger Detection And Enable Circuit

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US Patent:
6919811, Jul 19, 2005
Filed:
May 30, 2003
Appl. No.:
10/448603
Inventors:
Vladislav Potanin - San Jose CA, US
Elena Potanina - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G08B021/00
US Classification:
340657, 340660, 323304, 323311
Abstract:
A detection circuit is configured to detect the presence of a power source by comparing two input voltages (VIN, VIN). An example detection circuit is arranged, such that the first input voltage (VIN) may operate above the process limit for transistor breakdown, while the second input voltage (VIN) should be maintained below the transistor breakdown voltage. The detection circuit includes a built-in offset voltage (VOS) for hysteresis such that the detection signal is activated when VIN>VIN+VOS. The detection circuit is useful for providing an enable signal in a battery charger application. It is envisioned that the detection circuit is also useful in other applications where detection of a power source is required, and where detection of one voltage relative to another may be desired.

Current Sense Circuit

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US Patent:
7019581, Mar 28, 2006
Filed:
Jun 3, 2004
Appl. No.:
10/859627
Inventors:
Vladislav Potanin - San Jose CA, US
Elena Potanina - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03K 17/687
US Classification:
327427, 327543, 327 51
Abstract:
A method and circuit for tracking a load current and a load voltage to provide an output signal that is proportional to the load current. The circuit enables employment of high gate area (W/L) ratio for a current mirror type current sense circuit, while maintaining accuracy of a sense current. A tracking circuit tracks the load current and the load voltage providing equal biasing to a power pass transistor and a power sense transistor. The tracking circuit further supplies a gate voltage to a cascode transistor, which provides the output signal proportional to the load current. A trimming circuit allows adjustment of a current flowing through the cascode transistor enabling calibration of the circuit for variations of W/L ratio between the power pass transistor and power sense transistor due to manufacturing tolerances. Calibration may be performed during initial power-on and selected trimming transistors may be turned on or off.

Level Shifter That Provides High-Speed Operation Between Power Domains That Have A Large Voltage Difference

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US Patent:
7030678, Apr 18, 2006
Filed:
Feb 11, 2004
Appl. No.:
10/776834
Inventors:
Alexander Burinskiy - San Jose CA, US
Vladislav Potanin - San Jose CA, US
Elena Potanina - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03L 5/00
US Classification:
327333
Abstract:
The speed of a level shifter, which translates a first voltage in a first power domain to a second voltage in a second power domain, is increased by utilizing a first bipolar transistor to assist a first MOS transistor in pulling down the voltage on a first output node, and a second bipolar transistor to assist a second MOS transistor in pulling down the voltage on a second output node.

Controllable Current Trip-Point Detection Circuit

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US Patent:
7061210, Jun 13, 2006
Filed:
Apr 21, 2003
Appl. No.:
10/421004
Inventors:
Vladislav Potanin - San Jose CA, US
Elena Potanina - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H02J 7/00
US Classification:
320160
Abstract:
A current trip point detection circuit includes a transistor, a series of resistors, an amplifier, a comparator, and a series of switching circuits. The first transistor and the resistors are configured as an inverting gain stage. The amplifier cooperates with the first transistor to operate in a negative feedback arrangement. The gain in the feedback loop is adjusted by selective activation of additional transistors, where each additional transistor lowers the overall loop gain. The comparator is selectively coupled to a tap point in a voltage divider that is formed by resistors. The voltage divider tap point is selected to set a threshold for detection. The trip point is detected by the comparator, and may be adjusted between high and low trip points through the various configurations of the gain and voltage divider tap points via the switching circuits.

Trip-Point Detection Circuit

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US Patent:
7102415, Sep 5, 2006
Filed:
Mar 26, 2004
Appl. No.:
10/810120
Inventors:
Vladislav Potanin - San Jose CA, US
Elena Potanina - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03K 17/687
US Classification:
327427, 327434, 320162, 320164, 320165, 323284
Abstract:
A current is provided from a power source to a load through a pass circuit that is series coupled to a sense resistor. A current trip-point detection circuit is arranged to detect a change in the current that is provided to a load. The current trip-point detection circuit includes at least two resistors that are series coupled from the sense resistor to a current source. A comparator compares a sense voltage to a tap-point between the two resistors such that the comparator asserts a trip-point detection signal when the current to the load reaches a predetermined threshold. The sense voltage can correspond to the voltage across the load or some other voltage that is proportional to the voltage across the load. The circuit arrangement has a simplified design that sets the trip-point as a percentage of the maximum output current. The current level trip-point can be temperature compensated.

Current Regulation Circuit

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US Patent:
7161393, Jan 9, 2007
Filed:
Jun 3, 2004
Appl. No.:
10/860447
Inventors:
Vladislav Potanin - San Jose CA, US
Elena Potanina - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03B 1/00
US Classification:
327108, 327427, 361 79, 361 86, 361 92
Abstract:
A method and circuit for providing a regulated current to a load stabilized with respect to the load current, a load voltage, and a circuit temperature. The circuit includes a power pass device, a current sense device, a voltage sense amplifier, a reference device, a temperature sense device, and a current control device. In one embodiment, the current control device receives a first signal based on the sensed load current, a second signal based on the sensed load voltage, a third signal based on the circuit temperature, and a reference signal. A lesser of the second, third, and reference signals is selected and differentially combined with the first signal. A control signal is derived from the combination to control a regulation of the load current. In a further embodiment, an external signal may be provided to the current control device for stabilization with respect to an external parameter.

Method And System For Providing Precise Current Regulation And Limitation For A Power Supply

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US Patent:
7176664, Feb 13, 2007
Filed:
Apr 7, 2005
Appl. No.:
11/100826
Inventors:
Vladislav Potanin - San Jose CA, US
Elena Potanina - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G05F 1/40
US Classification:
323280, 323281
Abstract:
A method for providing precise current regulation and limitation for a power supply is provided. The method includes amplifying any difference between a load current signal and a current setting reference signal with a feedback loop amplifier to generate a feedback signal. A power output signal is generated based on the feedback signal. An output signal for the power supply is generated based on the power output signal. The load current signal and the current setting reference signal are generated based on the power output signal. An offset error signal is generated based on the load current signal and the current setting reference signal. A differential bias for the feedback loop amplifier is adjusted based on the offset error signal.

Dual-Source Cmos Battery Charger

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US Patent:
7253589, Aug 7, 2007
Filed:
Jul 9, 2004
Appl. No.:
10/888299
Inventors:
Vladislav Potanin - San Jose CA, US
Elena Potanina - San Jose CA, US
Khosrow Vijeh - Sunnyvale CA, US
Richard Dye - San Mateo CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H02J 7/00
H02J 7/04
H02J 1/00
US Classification:
320138, 307 80, 320144
Abstract:
A circuit for charging a battery by selecting among two available power sources while providing overcharging and temperature protection to the battery and managing a charging current is described. A power pass and sense circuit is arranged to provide charge voltage from either power source based on control voltages from a current/voltage control circuit, which receives control signals from a logic control and timer circuit, a sensed voltage from a current setting circuit and reference and temperature voltages from a voltage reference and thermo-sense circuit. Differential amplifiers controlling power pass transistors are turned on and off depending on a power source availability and selection. A power supply circuit provides global supply voltages to all subcircuits preventing reverse current to power sources and stable supply independent of a power source availability. A pair of transistors arranged to operate as body-switcher protect power pass and sense transistors against reverse bias current.
Vladislav Y Potanin from Granite Bay, CA, age ~64 Get Report