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Vladimir N Bolkhovsky

from Framingham, MA
Age ~75
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Also known as:
Vladimir Bolkhousky, Vlagimir Y
Phone and address:
45 Perry Henderson Dr, Framingham, MA 01701
(508) 877-3026
Related to:
Fred Scott Kogan, 60Nancy Epstein, 71Gary LeloupStephen Rogowsky, 72Michael Farrell, 36Valerie Salwen, 66
Connected to:
Daria Bolkhovsky, 71Brittney Bolkovac, 37Michele F Bolkovatz, 56Earl C Bolks, 100Robert M Bolkun, 42Natia Bolkvadze, 40Vakhtang Bolkvadze, 49Alicia L Boll, 42Harry E Boll, 93Jack T Boll, 73

Vladimir Bolkhovsky Phones & Addresses

  • 45 Perry Henderson Dr, Framingham, MA 01701 (508) 877-3026
  • Hyannis, MA
  • Poughkeepsie, NY
  • 45 Perry Henderson Dr, Framingham, MA 01701

Work

Company: Data evolution, llc May 2017 to Mar 2018 Position: Project engineer

Skills

System Administration • Account Management • Troubleshooting • Active Directory • Servers • Switches • Computer Hardware • Technical Support • Windows 7 • Network Administration • Html • Management • Networking • Crm • Leadership • Disaster Recovery • Team Leadership • Project Management

Languages

Russian

Interests

Social Services • Children • Mma • Economic Empowerment • Rock Climbing • Environment • Education • Science and Technology • Music • Disaster and Humanitarian Relief • Human Rights • Animal Welfare • Health

Industries

Information Technology And Services

Resumes

Resumes

Vladimir Bolkhovsky Photo 1

It Project Engineer

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Location:
2 Liberty Sq, Boston, MA 02109
Industry:
Information Technology And Services
Work:
Data Evolution, Llc May 2017 - Mar 2018
Project Engineer
Nsk & Associates, Inc. Feb 1, 2014 - May 2017
It Consultant at Nsk and Associates, Inc
Pc Healthstop Nov 2009 - Feb 2014
Technician
World Wide Technology Jun 2007 - Nov 2009
Field Service Technician
Coretelligent Jun 2007 - Nov 2009
It Project Engineer
Skills:
System Administration
Account Management
Troubleshooting
Active Directory
Servers
Switches
Computer Hardware
Technical Support
Windows 7
Network Administration
Html
Management
Networking
Crm
Leadership
Disaster Recovery
Team Leadership
Project Management
Interests:
Social Services
Children
Mma
Economic Empowerment
Rock Climbing
Environment
Education
Science and Technology
Music
Disaster and Humanitarian Relief
Human Rights
Animal Welfare
Health
Languages:
Russian

Publications

Us Patents

Bladed Silicon-On-Insulator Semiconductor Devices And Method Of Making

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US Patent:
6797547, Sep 28, 2004
Filed:
Oct 3, 2003
Appl. No.:
10/679220
Inventors:
Sheldon D. Haynie - Amherst NH
Steven L. Merchant - Bedford NH
Sameer P. Pendharkar - Richardson TX
Vladimir Bolkhovsky - Framingham MA
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2100
US Classification:
438149, 438479, 438517, 438310, 438311, 438412, 438282, 257347, 257349, 257507
Abstract:
A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post. The process can be used with conventional bulk silicon wafers and processes, and the blade devices can be integrated with conventional planar devices formed on other areas of the wafer.

Bladed Silicon-On-Insulator Semiconductor Devices And Method Of Making

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US Patent:
6800917, Oct 5, 2004
Filed:
Dec 17, 2002
Appl. No.:
10/321423
Inventors:
Sheldon D. Haynie - Amherst NH
Steven L. Merchant - Bedford NH
Sameer P. Pendharkar - Richardson TX
Vladimir Bolkhovsky - Framingham MA
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2176
US Classification:
257506, 257524, 257E21553, 257E21564
Abstract:
A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post. The process can be used with conventional bulk silicon wafers and processes, and the blade devices can be integrated with conventional planar devices formed on other areas of the wafer.

Method To Manufacture Ldmos Transistors With Improved Threshold Voltage Control

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US Patent:
7141455, Nov 28, 2006
Filed:
Nov 12, 2003
Appl. No.:
10/712455
Inventors:
Binghua Hu - Plano TX, US
Howard S. Lee - Plano TX, US
Henry L. Edwards - Garland TX, US
John Lin - Chelmsford MA, US
Vladimir N. Bolkhovsky - Framingham MA, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/332
US Classification:
438135, 438306, 438305
Abstract:
A double diffused region (), (), () is formed in an epitaxial layer (). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer () is formed on the epitaxial layer () and gate structures (), () are formed over the dielectric layer ().

Premature Breakdown In Submicron Device Geometries

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US Patent:
7195965, Mar 27, 2007
Filed:
Nov 22, 2002
Appl. No.:
10/302256
Inventors:
John Lin - Chelmsford MA, US
Philip L. Hower - Concord MA, US
Taylor R. Efland - Richardson TX, US
Sameer Pendharkar - Richardson TX, US
Vladimir Bolkhovsky - Framingham MA, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/8248
US Classification:
438202, 438309
Abstract:
The concept of the present invention describes a semiconductor device with a junction between a lightly doped region and a heavily doped region , wherein the junction has an elongated portion and curved portions. The doping concentration of the lightly doped region is configured so that it exhibits higher resistivity in the proximity of the curved portion by an amount suitable to lower the electric field strength during device operation and thus to offset the increased field strength caused by the curved portion. As a consequence, the device breakdown voltage in the curved junction portion becomes equal to or greater than the breakdown voltage in the linear portion.

Method To Manufacture Ldmos Transistors With Improved Threshold Voltage Control

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US Patent:
7696049, Apr 13, 2010
Filed:
Oct 24, 2006
Appl. No.:
11/552198
Inventors:
Binghua Hu - Plano TX, US
Howard S. Lee - Plano TX, US
Henry L. Edwards - Garland TX, US
John Lin - Chelmsford MA, US
Vladimir N. Bolkhovsky - Framingham MA, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/00
US Classification:
438289, 438297, 438301
Abstract:
A double diffused region (), (), () is formed in a semiconductor substrate or in an epitaxial layer () formed on the semiconductor substrate. The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to the hard bake process, a heavy implant species such as arsenic is implanted into the epitaxial layer. During subsequent processing, such as during LOCOS formation, a double diffused region is formed by a thermal anneal. A dielectric layer () is formed on the epitaxial layer () and gate structures (), () are formed over the dielectric layer ().

Method For Manufacturing A Semiconductor Device Using Dummy Openings In A Photoresist Material And An Ldmos Device Manufactured In Accordance With The Method

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US Patent:
20040079974, Apr 29, 2004
Filed:
Oct 24, 2002
Appl. No.:
10/279316
Inventors:
John Lin - Chelmsford MA, US
Phil Hower - Concord MA, US
Vladimir Bolkhovsky - Framingham MA, US
Binghua Hu - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L021/336
H01L021/8234
H01L029/76
H01L031/062
H01L031/119
US Classification:
257/288000, 438/197000, 438/276000
Abstract:
The present invention provides a method for manufacturing a semiconductor device, an associated method for manufacturing an integrated circuit, and an LDMOS device manufactured in accordance with the method for manufacturing the semiconductor device. The method for manufacturing the semiconductor device, in one embodiment, may include depositing a layer of photoresist material over a substrate and creating an active device opening having sidewall angles associated therewith through the photoresist material. Additionally, the method may include forming a dummy opening through the photoresist material, wherein the dummy opening is located proximate the active device opening to reduce a shrinkage of the photoresist between the dummy opening and the active device opening and thereby inhibit nonuniform distortion of the sidewall angles.

Bladed Silicon-On-Insulator Semiconductor Devices And Method Of Making

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US Patent:
20040222485, Nov 11, 2004
Filed:
Jun 4, 2004
Appl. No.:
10/861797
Inventors:
Sheldon Haynie - Amherst NH, US
Steven Merchant - Bedford NH, US
Sameer Pendharkar - Richardson TX, US
Vladimir Bolkhovsky - Framingham MA, US
International Classification:
H01L027/01
US Classification:
257/506000
Abstract:
A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post. The process can be used with conventional bulk silicon wafers and processes, and the blade devices can be integrated with conventional planar devices formed on other areas of the wafer.

Electromigration-Resistant Via Structure

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US Patent:
60966378, Aug 1, 2000
Filed:
Jul 28, 1998
Appl. No.:
9/124198
Inventors:
Tirunelveli S. Sriram - Maynard MA
Ann C. Westerheim - Westford MA
John J. Maziarz - Sutton MA
Vladimir Bolkhovsky - Framingham MA
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
H01L 214763
US Classification:
438643
Abstract:
A method is described for forming an electromigration-resistant (ER) intermetallic region beneath and adjacent a conductive plug in a via. Preferably the ER region is formed of a sintered intermetallic compound of Al and Ti, and the conductive plug is formed of W.
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Vladimir N Bolkhovsky from Framingham, MA, age ~75 Get Report