Resumes
Resumes
Viktor Zekeriya Phones & Addresses
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Bal Harbour, FL
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35 Edge Rd, Atherton, CA 94027 (650) 325-4159
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Menlo Park, CA
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350 Sequoia Ave, Palo Alto, CA 94306 (650) 325-1699 (650) 325-4159
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Mountain View, CA
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Sunnyvale, CA
Publications
Us Patents
Globally Planarized Backend Compatible Thin Film Resistor Contact/Interconnect Process
View pageUS Patent:
6607962, Aug 19, 2003
Filed:
Aug 9, 2001
Appl. No.:
09/925945
Inventors:
Viktor Zekeriya - Atherton CA
Khanh Tran - Milpitas CA
Khanh Tran - Milpitas CA
Assignee:
Maxim Integrated Products, Inc. - Sunnyvale CA
International Classification:
H01L 2120
US Classification:
438384, 438382, 438597, 438672, 438675
Abstract:
A method of forming a thin film resistor contact incorporates an etch-stop material to protect the underlying thin film resistor from a subsequent dry etching process to form a contact opening to the thin film resistor. More specifically, the method includes forming a thin film resistor, forming a first dielectric layer over the thin film resistor, forming a first opening through the first dielectric layer to expose an underlying portion of the thin film resistor, forming an etch-stop within the first opening of the first dielectric layer, forming a second dielectric layer over the etch-stop and the first dielectric layer, forming a second opening through the second dielectric layer to expose the underlying portion of the etch-stop, and forming a metal plug within the second contact opening, wherein the metal plug is in electrical contact with the thin film resistor by way of the etch-stop. Alternatively, in the case of an insulating etch-stop, the second opening through the dielectric layer is through the etch-stop, and forming a metal plug within the second contact opening, wherein the metal plug is in direct electrical contact with the thin film resistor.
Integrating Multiple Thin Film Resistors
View pageUS Patent:
6855585, Feb 15, 2005
Filed:
Oct 31, 2001
Appl. No.:
10/002429
Inventors:
Alexander Kalnitsky - Portland OR, US
Joseph Paul Elull - San Jose CA, US
Ralph Wall - Beaverton OR, US
Robert F. Scheer - Portland OR, US
Jonathan Herman - San Jose CA, US
Glenn Nobinger - Santa Clara CA, US
Viktor Zekeriya - Atherton CA, US
Joseph Paul Elull - San Jose CA, US
Ralph Wall - Beaverton OR, US
Robert F. Scheer - Portland OR, US
Jonathan Herman - San Jose CA, US
Glenn Nobinger - Santa Clara CA, US
Viktor Zekeriya - Atherton CA, US
Assignee:
Maxim Integrated Products, Inc. - Sunnyvale CA
International Classification:
H01L021/302
US Classification:
438171, 438330, 438697, 438700
Abstract:
A method for forming multiple resistors on a substrate. The method initially includes providing a first resistor on the substrate. A first dielectric layer is deposited, patterned, and selectively etched over the first resistor. Second resistor material is provided over the first dielectric layer. Furthermore, landing pad material is provided over the second resistor material. The landing pad material and the second resistor material are then selectively etched. The selective etching forms contacts for the first resistor in a first region, and forms a second resistor and associated contacts in a second region.
Method Of Removing A Sacrificial Emitter Feature In A Bicmos Process With A Super Self-Aligned Bjt
View pageUS Patent:
6962842, Nov 8, 2005
Filed:
Mar 6, 2003
Appl. No.:
10/382597
Inventors:
Alexander Kalnitsky - San Francisco CA, US
Sang H. Park - Portland OR, US
Viktor Zekeriya - Atherton CA, US
Larry Wang - San Jose CA, US
Sang H. Park - Portland OR, US
Viktor Zekeriya - Atherton CA, US
Larry Wang - San Jose CA, US
Assignee:
Maxim Integrated Products, Inc. - Sunnyvale CA
International Classification:
H01L021/8238
H01L029/00
H01L029/00
US Classification:
438202, 438320, 438322, 438338, 438353, 257554, 257560, 257564
Abstract:
A method of removing a sacrificial emitter feature in a bipolar complementary metal oxide semiconductor (BICMOS) process with a super self-aligned bipolar junction transistor (BJT) is disclosed. According to the new method, a mask layer, such as an oxide deposited using high density plasma (HDP) techniques, is deposited over an extrinsic base layer and over a sacrificial emitter structure. Because of the particular characteristic of the HDP oxide, the deposition of HDP oxide forms a triangular-like structure over the sacrificial emitter structure having a maximum thickness less than the thickness of the HDP oxide over the extrinsic base layer. This facilitates the complete removal of the HDP oxide above the sacrificial emitter layer without the complete removal of the HDP oxide above the extrinsic base layer. This allows the removal of the sacrificial emitter structure while the remaining HDP oxide, serving as a mask, protects the underlying extrinsic base layer.
Plasma Systems With Magnetic Filter Devices To Alter Film Deposition/Etching Characteristics
View pageUS Patent:
20070246354, Oct 25, 2007
Filed:
Apr 19, 2006
Appl. No.:
11/407441
Inventors:
Joseph Ellul - San Jose CA, US
Melvin Schmidt - San Jose CA, US
Viktor Zekeriya - Atherton CA, US
Rajiv Patel - San Jose CA, US
Jack Kelly - San Jose CA, US
Melvin Schmidt - San Jose CA, US
Viktor Zekeriya - Atherton CA, US
Rajiv Patel - San Jose CA, US
Jack Kelly - San Jose CA, US
International Classification:
C23C 14/00
US Classification:
204298020
Abstract:
Plasma systems with magnetic filter devices to alter film deposition/etching characteristics by altering the effective magnetic field distribution. The magnetic filter devices are placed between the magnet or magnets and a target, typically a semiconductor wafer, and selected and configured to alter the magnetic field to obtain the desired processing results. For deposition, the magnetic filter may be chosen to provide more uniform deposition, to provide increased deposition rates at or adjacent the edges of a wafer to compensate for increased etching rates at the edges of a wafer in a subsequent etching or polishing process. For annealing and doping, the magnetic field may be altered to provide more uniform equivalent annealing or doping across the wafer. Various applications are disclosed.
Plasma Systems With Magnetic Filter Devices To Alter Film Deposition/Etching Characteristics
View pageUS Patent:
20080296143, Dec 4, 2008
Filed:
Aug 14, 2008
Appl. No.:
12/191505
Inventors:
Joseph Paul Ellul - San Jose CA, US
Melvin C. Schmidt - San Jose CA, US
Viktor Zekeriya - Atherton CA, US
Rajiv L. Patel - San Jose CA, US
Jack Kelly - San Jose CA, US
Melvin C. Schmidt - San Jose CA, US
Viktor Zekeriya - Atherton CA, US
Rajiv L. Patel - San Jose CA, US
Jack Kelly - San Jose CA, US
Assignee:
MAXIM INTEGRATED PRODUCTS, INC. - Sunnyvale CA
International Classification:
C23C 14/34
H05H 1/46
H05H 1/46
US Classification:
204156
Abstract:
Plasma systems with magnetic filter devices to alter film deposition/etching characteristics by altering the effective magnetic field distribution. The magnetic filter devices are placed between the magnet or magnets and a target, typically a semiconductor wafer, and selected and configured to alter the magnetic field to obtain the desired processing results. For deposition, the magnetic filter may be chosen to provide more uniform deposition, to provide increased deposition rates at or adjacent the edges of a wafer to compensate for increased etching rates at the edges of a wafer in a subsequent etching or polishing process. For annealing and doping, the magnetic field may be altered to provide more uniform equivalent annealing or doping across the wafer. Various applications are disclosed.
Method Of Modifying Properties Of Deposited Thin Film Material
View pageUS Patent:
6358809, Mar 19, 2002
Filed:
Jan 16, 2001
Appl. No.:
09/764812
Inventors:
Glenn Nobinger - Santa Clara CA
Alexander Kalnitsky - Portland OR
Melvin Schmidt - San Jose CA
Jonathan Herman - San Jose CA
Viktor Zekeriya - Palo Alto CA
Vijaykumar Ullal - Saratoga CA
Daniel H. Rosenblatt - San Carlos CA
Joseph P. Ellul - San Jose CA
Alexander Kalnitsky - Portland OR
Melvin Schmidt - San Jose CA
Jonathan Herman - San Jose CA
Viktor Zekeriya - Palo Alto CA
Vijaykumar Ullal - Saratoga CA
Daniel H. Rosenblatt - San Carlos CA
Joseph P. Ellul - San Jose CA
Assignee:
Maxim Integrated Products, Inc. - Sunnyvale CA
International Classification:
H01L 2120
US Classification:
438382, 438238, 438385
Abstract:
A method of modifying a layer of thin film composite material to achieve one or more desired properties for the thin film layer which cannot be achieved by heat treatment at all practical temperatures of operation allowable by particular integrated circuit processes. In particular, the thin film composite material is subjected to an ion implantation process. Depending on the doping species, the doping concentration, the doping energy, and other ion implantation parameters, one or more properties of the deposited thin film resistive layer can be modified. Such properties may include electrical, optical, thermal and physical properties. For instance, the sheet resistance and/or the temperature coefficient of resistance of the thin film composite material may be increased or decreased by appropriately implanting ions into the material. The ion implantation can be applied globally in order to modify one or more properties of the entire deposited thin film composite layer. Alternatively, the ion implantation can be applied regionally in order to modify the thin film composite material at a first region, not modify the thin film composite material at a second region, and/or modify the thin film composite material in another way at a third region.