Search

Vijay Mohan Sajja

from Fremont, CA
Age ~67
Get Report
Also known as:
Vijay M Sajja, Vijay Te Sajja, Vijay Mohan, Vijay Mohan Sajjy, Vijay M Sajjy, Vijay M Rajarajeswari, Bay Sajja, Sajja Vijay Mohan, Sajja Vi Bay, Sajja Bay
Phone and address:
5322 Diamond Cmn, Fremont, CA 94555
Related to:
Smita M Samant, 55Sunita SamantKalyan Sajja, 37Vikram Samant, 33Ameya Samant, 38Rajarajeswari Sajja, 64
Connected to:
Deepthi Sajja, 38Pramod K Sajja, 52Prasad Sajja, 70Ahmad S Sajjad, 51Amir Sajjad, 45Khurram Sajjad, 48Laila Sajjad, 51Malik M Sajjad, 51Nabila Sajjad, 35Qazzafi Sajjad, 49

Vijay Sajja Phones & Addresses

  • 5322 Diamond Cmn, Fremont, CA 94555
  • 212 Montevideo Ct, Fremont, CA 94539 (510) 573-0924 (510) 770-8624
  • Alameda, CA

Resumes

Resumes

Vijay Sajja Photo 1

Vijay Sajja

View page
Location:
San Francisco Bay Area
Industry:
Computer Software
Vijay Sajja Photo 2

Director, Packaging And Reliability

View page
Location:
San Francisco, CA
Industry:
Electrical/Electronic Manufacturing
Work:
Nevada Nanotech Systems Inc
Director, Packaging and Reliability
Xperi Corporation Aug 2011 - Apr 2016
Manager
Lightwire and Aod India 2009 - Jul 2011
Consultant
Crossbow Technology 2004 - 2008
Director, Operations
Validity Sensors, Inc. 2002 - 2004
Director, Operations
Education:
Syracuse University 1980 - 1982
Master of Science, Masters, Materials Science Indian Institute of Technology, Kharagpur 1974 - 1979
Bachelors, Bachelor of Science
Skills:
Semiconductors
Manufacturing
Product Development
Program Management
Start Ups
Engineering Management
Failure Analysis
Product Management
Electronics
Ic

Business Records

Name / Title
Company / Classification
Phones & Addresses
Vijay K. Sajja
Director, President, President, Secretary, Treasurer
Evergent Technologies, Inc
2360 Corporate Cir, Henderson, NV 89074
12469 Robleda Rd, Los Altos, CA 94022

Publications

Us Patents

Solder Plating Process And Semiconductor Product

View page
US Patent:
45899622, May 20, 1986
Filed:
Jun 3, 1985
Appl. No.:
6/740170
Inventors:
Vijay M. Sajja - Fremont CA
Ranjan Mathew - San Jose CA
Jagdish Belane - Cupertino CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
C25D 502
C25D 534
US Classification:
204 15
Abstract:
A method for solder plating metal leads in plastic semiconductor packages comprises cleaning the leads followed by electroplating tin or a tin/lead alloy onto the leads. The cleaning is effected with a non-corrosive solution which is either a carboxylic acid, a hydroxycarboxylic acid, or a combination of both. The electroplating solution is a sulfonic acid or citric acid based system, including suitable tin salts and/or lead salts. A sequestering agent may be used to inhibit the corrosive effect of the electroplating bath.

Circuit Board For High Pin Count Surface Mount Pin Grid Arrays

View page
US Patent:
54009480, Mar 28, 1995
Filed:
Feb 2, 1994
Appl. No.:
8/190795
Inventors:
Vijay M. Sajja - Fremont CA
Siamak Jonaidi - San Jose CA
Assignee:
Aptix Corporation - San Jose CA
International Classification:
B23K 3102
H05K 334
US Classification:
2281801
Abstract:
A method for fabricating a printed circuit board for high pin count surface mount pin grid arrays is provided where surface mount pads for soldering a surface mount pin grid array package are isolated by solder mask layers. The printed circuit board is laminated with one or more solder mask layers containing apertures therein to expose the surface mount pad locations.

Circuit Board For High Pin Count Surface Mount Pin Grid Arrays

View page
US Patent:
53130219, May 17, 1994
Filed:
Sep 18, 1992
Appl. No.:
7/947106
Inventors:
Vijay M. Sajja - Fremont CA
Siamak Jonaidi - San Jose CA
Assignee:
Aptix Corporation - San Jose CA
International Classification:
H05K 103
US Classification:
174260
Abstract:
A printed circuit board is provided with surface mount pads for soldering a surface mount pin grid array package. The printed circuit board is laminated with one or more solder mask layers containing apertures therein to expose the surface mount pad locations.

Solder Composition For Thin Coatings

View page
US Patent:
44865112, Dec 4, 1984
Filed:
Jun 27, 1983
Appl. No.:
6/508376
Inventors:
Yung-Shih Chen - San Jose CA
Jagdish G. Belani - Cupertino CA
Vijay Sajja - Sunnyvale CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H02B 104
H05K 328
US Classification:
428620
Abstract:
A solder composition of 10 to 40 percent tin, with the balance lead, for use in thin layers of 50 to 500 microinches on copper integrated circuit leads so as to resist the formation of intermetallics when later heated.
Control profile
Vijay Mohan Sajja from Fremont, CA, age ~67 Get Report