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Ugonna C Echeruo

from Hillsboro, OR
Age ~50
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Also known as:
Ligonna C Echeruo, C Echeruo
Phone and address:
333 NW Malia Ln, Beaverton, OR 97124
Related to:
June McintoshMarshalee C Mcintosh, 32Janeen Mcintosh, 41Ike EcheruoAdamma Echeruo, 42
Connected to:
Ralindu Z Echetebu, 124Adrian R Echevarria, 47Amber R Echevarria, 30Arlene Echevarria, 35Belinda Echevarria, 55Benjamin Echevarria, 55Carlos A Echevarria, 47Catalina Echevarria, 65Cristal Echevarria, 36Destiny Echevarria, 33

Ugonna Echeruo Phones & Addresses

  • 333 NW Malia Ln, Hillsboro, OR 97124
  • 5205 Halcyon Dr, Worcester, MA 01606
  • Cambridge, MA
  • Harvard, MA
  • Jamesville, NY

Work

Company: Intel corporation Sep 2001 Position: Computer architect

Education

Degree: Masters School / High School: Massachusetts Institute of Technology 1993 to 1998 Specialities: Engineering

Skills

Processors • Computer Architecture • Microprocessors • Verilog • Soc • Vlsi • Asic • Hardware Architecture • Rtl Design • Microarchitecture • Software Engineering • High Performance Computing • Low Power Design • Very Large Scale Integration

Industries

Semiconductors

Resumes

Resumes

Ugonna Echeruo Photo 1

Computer Architect

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Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Semiconductors
Work:
Intel Corporation
Computer Architect
Opelin 1999 - 2001
Design Engineer
Intel Corporation 1998 - 1999
Design Engineer
Education:
Massachusetts Institute of Technology 1993 - 1998
Masters, Engineering
Skills:
Processors
Computer Architecture
Microprocessors
Verilog
Soc
Vlsi
Asic
Hardware Architecture
Rtl Design
Microarchitecture
Software Engineering
High Performance Computing
Low Power Design
Very Large Scale Integration

Publications

Us Patents

Method And Apparatus For Protecting Tlb's Vpn From Soft Errors

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US Patent:
7607048, Oct 20, 2009
Filed:
Dec 30, 2004
Appl. No.:
11/026633
Inventors:
Ugonna C. Echeruo - Worcester MA, US
George Z. Chrysos - Milford MA, US
John H. Crawford - Saratoga CA, US
Shubhendu S. Mukherjee - Framingham MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 11/00
US Classification:
714 42, 714718
Abstract:
A method and apparatus for protecting a TLB's VPN from soft errors is described. On a TLB lookup, the incoming virtual address is used to CAM the TLB VPN. In parallel with this CAM operation, parity is computed on the incoming virtual address for the possible page sizes supported by the processor. If a matching VPN is found in the TLB, its payload is read out. The encoded page size is used to select which of the set of pre-computed virtual address parity to compare with the stored parity bit in the TLB entry. This has the advantage of removing the computation of parity on the TLB VPN from the critical path of the TLB lookup. Instead it is now in the TLB fill path.

Converting Merge Buffer System-Kill Errors To Process-Kill Errors

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US Patent:
7380169, May 27, 2008
Filed:
Sep 24, 2004
Appl. No.:
10/948904
Inventors:
Tryggve Fossum - Northborough MA, US
Yaron Shragai - Natick MA, US
Ugonna Echeruo - Worcester MA, US
Shubhendu S. Mukherjee - Framingham MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 11/00
US Classification:
714 36
Abstract:
An apparatus includes a buffer that collects store instruction information associated with one or more processes. The collected store instruction information includes data and addresses where the data are to be stored. The apparatus also includes a buffer control that drains the buffer of store instructions associated with a first process before it collects store instructions associated with a second process.

Method And Apparatus For Implementing Memory Order Models With Order Vectors

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US Patent:
20060026371, Feb 2, 2006
Filed:
Jul 30, 2004
Appl. No.:
10/903675
Inventors:
George Chrysos - Milford MA, US
Ugonna Echeruo - Worcester MA, US
James Vash - North Grafton MA, US
International Classification:
G06F 12/00
US Classification:
711158000
Abstract:
In one embodiment of the present invention, a method includes generating a first order vector corresponding to a first entry in an operation order queue that corresponds to a first memory operation, and preventing a subsequent memory operation from completing until the first memory operation completes. In such a method, the operation order queue may be a load queue or a store queue, for example. Similarly, an order vector may be generated for an entry of a first operation order queue based on entries in a second operation order queue. Further, such an entry may include a field to identify an entry in the second operation order queue. A merge buffer may be coupled to the first operation order queue and produce a signal when all prior writes become visible.

Memory Side Prefetch Architecture For Improved Memory Bandwidth

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US Patent:
20230091205, Mar 23, 2023
Filed:
Sep 20, 2021
Appl. No.:
17/479582
Inventors:
- Santa Clara CA, US
Ugonna Echeruo - Hillsboro OR, US
Eduard Roytman - Newton Centre MA, US
Krishnakanth Sistla - Portland OR, US
Joseph Nuzman - Haifa, IL
Brinda Ganesh - Portland OR, US
Meenakshisundaram Chinthamani - Hillsboro OR, US
Yen-Cheng Liu - Portland OR, US
Sai Prashanth Muralidhara - Portland OR, US
Hanna Alam - Jish, IL
Narasimha Sridhar Srirangam - Santa Clara CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/0862
G06F 13/28
Abstract:
Methods and apparatus relating to memory side prefetch architecture for improved memory bandwidth are described. In an embodiment, logic circuitry transmits a Direct Memory Controller Prefetch (DMCP) request to cause a prefetch of data from memory. A memory controller receives the DMCP request and issues a plurality of read operations to the memory in response to the DMCP request. Data read from the memory is stored in a storage structure in response to the plurality of read operations. Other embodiments are also disclosed and claimed.

Apparatus, Method, And System For Enhanced Data Prefetching Based On Non-Uniform Memory Access (Numa) Characteristics

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US Patent:
20200233806, Jul 23, 2020
Filed:
Apr 1, 2020
Appl. No.:
16/837833
Inventors:
- Santa Clara CA, US
Ibrahim Hur - Portland OR, US
Ugonna Echeruo - Hillsboro OR, US
Stijn Eyerman - Evergem, BE
Kristof Du Bois - Aalst, BE
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/0862
Abstract:
Apparatus, method, and system for enhancing data prefetching based on non-uniform memory access (NUMA) characteristics are described herein. An apparatus embodiment includes a system memory, a cache, and a prefetcher. The system memory includes multiple memory regions, at least some of which are associated with different NUMA characteristic (access latency, bandwidth, etc.) than others. Each region is associated with its own set of prefetch parameters that are set in accordance to their respective NUMA characteristics. The prefetcher monitors data accesses to the cache and generates one or more prefetch requests to fetch data from the system memory to the cache based on the monitored data accesses and the set of prefetch parameters associated with the memory region from which data is to be fetched. The set of prefetcher parameters may include prefetch distance, training-to-stable threshold, and throttle threshold.

Apparatus, Method, And System For Enhanced Data Prefetching Based On Non-Uniform Memory Access (Numa) Characteristics

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US Patent:
20200004684, Jan 2, 2020
Filed:
Jun 29, 2018
Appl. No.:
16/024527
Inventors:
- Santa Clara CA, US
Ibrahim Hur - Portland OR, US
Ugonna Echeruo - Hillsboro OR, US
Stijn Eyerman - Evergem, BE
Kristof Du Bois - Aalst, BE
International Classification:
G06F 12/0862
Abstract:
Apparatus, method, and system for enhancing data prefetching based on non-uniform memory access (NUMA) characteristics are described herein. An apparatus embodiment includes a system memory, a cache, and a prefetcher. The system memory includes multiple memory regions, at least some of which are associated with different NUMA characteristic (access latency, bandwidth, etc.) than others. Each region is associated with its own set of prefetch parameters that are set in accordance to their respective NUMA characteristics. The prefetcher monitors data accesses to the cache and generates one or more prefetch requests to fetch data from the system memory to the cache based on the monitored data accesses and the set of prefetch parameters associated with the memory region from which data is to be fetched. The set of prefetcher parameters may include prefetch distance, training-to-stable threshold, and throttle threshold.

Hardware Apparatuses And Methods Relating To Elemental Register Accesses

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US Patent:
20160188334, Jun 30, 2016
Filed:
Dec 24, 2014
Appl. No.:
14/582784
Inventors:
- Santa Clara CA, US
Ugonna Echeruo - Hillsboro OR, US
George Chrysos - Portland OR, US
Naveen Mellempudi - Bangalore, IN
International Classification:
G06F 9/30
Abstract:
Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.
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Ugonna C Echeruo from Hillsboro, OR, age ~50 Get Report