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Tyler C Gomm

from Smithfield, UT
Age ~34
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Related to:
Taunia Lindley, 57Christian Gomm Tyler, 34Steven Craig Gomm, 46Cooper GommJennifer Miller, 46Tyler Schild, 37David Gomm, 44Kathy Gomm, 73
Connected to:
Ben C Gomm, 38David C Gomm, 40Jonathan T Gomm, 74Laura E Gomm, 49Michael T Gomm, 43Cheyenne Gomma, 42Andrew R Gomme, 61Cheryl L Gommel, 66Jonathan C Gommel, 36Linda C Gommel, 75

Tyler Gomm Phones & Addresses

  • Smithfield, UT
  • 438 Kent Dr, N Salt Lake, UT 84054
  • North Salt Lake, UT
  • 11753 S Brisbane Dr, Sandy, UT 84094
  • Eagle, ID
  • Gilbert, AZ

Work

Company: Mrc global Position: Emt

Industries

Oil & Energy

Resumes

Resumes

Tyler Gomm Photo 1

Tyler Gomm

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Location:
11149 south Sandy Gulch Rd, Sandy, UT 84094
Industry:
Oil & Energy
Work:
Mrc Global
Emt

Publications

Us Patents

Ultrasonic Flow Metering System

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US Patent:
6487916, Dec 3, 2002
Filed:
Feb 2, 2000
Appl. No.:
09/496787
Inventors:
Tyler J. Gomm - Meridian ID
Nancy C. Kraft - Idaho Falls ID
Jason A. Mauseth - Pocatello ID
Larry D. Phelps - Pocatello ID
Steven C. Taylor - Idaho Falls ID
Assignee:
Bechtel BXWT Idaho, LLC - Idaho Falls ID
International Classification:
G01F 166
US Classification:
7386129, 7386128, 7386127
Abstract:
A system for determining the density, flow velocity, and mass flow of a fluid comprising at least one sing-around circuit that determines the velocity of a signal in the fluid and that is correlatable to a database for the fluid. A system for determining flow velocity uses two of the inventive circuits with directional transmitters and receivers, one of which is set at an angle to the direction of flow that is different from the others.

Method And Apparatus For Determining Digital Delay Line Entry Point

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US Patent:
6556489, Apr 29, 2003
Filed:
Aug 6, 2001
Appl. No.:
09/923136
Inventors:
Tyler J. Gomm - Meridian ID
Aaron M. Schoenfeld - Boise ID
Travis E. Dirkes - Boise ID
Ross E. Dermott - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365194, 365233, 36518912, 365236, 327156
Abstract:
A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, a counter is coupled to the phase detector of the DLL to track the entry point of the delay line. The entry point information can be taken over a variety of voltages, temperatures, and frequencies to characterize the DLL. The counter may be located on the synchronous device or external to the device.

Method For Noise And Power Reduction For Digital Delay Lines

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US Patent:
6586979, Jul 1, 2003
Filed:
Mar 23, 2001
Appl. No.:
09/815465
Inventors:
Tyler J. Gomm - Meridian ID
Travis E. Dirkes - Bozeman MT
Ross E. Dermott - Bozeman MT
Daniel R. Loughmiller - Boise ID
Scott E. Smith - Plano TX
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H03D 324
US Classification:
327161, 327158, 327236
Abstract:
A delay circuit that includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.

Ultrasonic Fluid Quality Sensor System

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US Patent:
6634239, Oct 21, 2003
Filed:
Aug 6, 2002
Appl. No.:
10/213595
Inventors:
Tyler J. Gomm - Meridian ID
Nancy C. Kraft - Idaho Falls ID
Larry D. Phelps - Pocatello ID
Steven C. Taylor - Idaho Falls ID
Assignee:
Bechtel BWXT Idaho, LLC - Idaho Falls ID
International Classification:
G01F 166
US Classification:
7386127, 7386129
Abstract:
A system for determining the composition of a multiple-component fluid and for determining linear flow comprising at least one sing-around circuit that determines the velocity of a signal in the multiple-component fluid and that is correlatable to a database for the multiple-component fluid. A system for determining flow uses two of the inventive circuits, one of which is set at an angle that is not perpendicular to the direction of flow.

Dynamically Centered Setup-Time And Hold-Time Window

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US Patent:
6661717, Dec 9, 2003
Filed:
May 30, 2002
Appl. No.:
10/158607
Inventors:
Tyler J. Gomm - Meridian ID
Aaron M. Schoenfeld - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365194, 365233, 365241
Abstract:
An apparatus and method for dynamically centering a setup-time and hold-time window. An access window defined by a setup-time and a hold-time is determined. A determination is made whether the access window is centered about a centerline. The centerline is a point between a predetermined setup-time limit and a predetermined hold-time limit. A dynamic access window centering process is performed in response to the determination that the access window is not centered about the centerline. The dynamic access window centering process includes: determining that the access window has shifted from the centerline; and providing at least one of a dynamic delay and a dynamic speed-up of the access window based upon the determination that the access window has shifted from the centerline.

Variable Delay Circuit And Method, And Delay Locked Loop, Memory Device And Computer System Using Same

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US Patent:
6727734, Apr 27, 2004
Filed:
Oct 9, 2002
Appl. No.:
10/268225
Inventors:
Tyler J. Gomm - Meridian ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H03L 706
US Classification:
327156, 327158
Abstract:
A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input clock signal enters the delay circuit is adjusted to vary the delay of an output clock signal. In another embodiment, the point in the delay circuit from which the output clock signal exits the delay circuit is adjusted to vary the delay of an output clock signal. In either case, the polarity of the input or output clock signal is adjusted as the delay is adjusted so there are always an even number of inverters or inverting gates between an input terminal to which the input clock signal is applied and an output terminal from which the output clock signal is generated.

Controlling A Delay Lock Loop Circuit

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US Patent:
6728163, Apr 27, 2004
Filed:
Aug 23, 2002
Appl. No.:
10/226782
Inventors:
Tyler J. Gomm - Meridian ID
Ross E. Dermott - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365233, 365236, 365194
Abstract:
A method and apparatus is provided for performing a filter control of a delay lock loop circuit. A coarse delay and/or a fine delay are implemented upon a reference signal based upon a phase shift between the reference signal and a feedback signal. A synchronized output signal is generated based upon the coarse delay and the fine delay. The apparatus of the present invention includes a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop comprises a filter to provide a filter response to the phase difference. The filter response is capable of providing a coarse delay and/or a fine delay.

Variable Delay Circuit And Method, And Delay Locked Loop, Memory Device And Computer System Using Same

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US Patent:
6735148, May 11, 2004
Filed:
Oct 15, 2002
Appl. No.:
10/272245
Inventors:
Tyler J. Gomm - Meridian ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 800
US Classification:
365233, 365194, 36523008
Abstract:
A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input clock signal enters the delay circuit is adjusted to vary the delay of an output clock signal. In another embodiment, the point in the delay circuit from which the output clock signal exits the delay circuit is adjusted to vary the delay of an output clock signal. In either case, the polarity of the input or output clock signal is adjusted as the delay is adjusted so there are always an even number of inverters or inverting gates between an input terminal to which the input clock signal is applied and an output terminal from which the output clock signal is generated.
Control profile
Tyler C Gomm from Smithfield, UT, age ~34 Get Report