US Patent:
20110147897, Jun 23, 2011
Inventors:
Alejandro Varela - Phoenix AZ, US
Troy L. Harling - Gresham OR, US
Daniel E. Vanlare - Phoenix AZ, US
International Classification:
H01L 23/544
H01L 21/78
US Classification:
257620, 438462, 257E23179, 257E21599
Abstract:
Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on the wafer can be increased, relative to a standard perpendicular grid. By adding additional registration marks, an increase in flexibility of where each row/column of fields can be printed is enabled. This increased level of freedom in-turn allows for the optimization of the number of die that each row/column can contain, and translates directly into an increase in the number of yielding die per wafer. In addition, techniques are provided that allow for the dicing of individual die in a non-Cartesian coordinated manner. However, conventional singulation techniques can be used as well, given attention to the offset grid lines.