Search

Terri Couteau Phones & Addresses

  • Bull Shoals, AR
  • Corpus Christi, TX
  • 115 Norma Jean Blvd, Smithville, TX 78957 (512) 581-1782
  • 331 La Reata Trl, Smithville, TX 78957 (512) 360-4996 (512) 360-5123
  • 2292 Fm 535, Rosanky, TX 78953 (830) 839-4215
  • Bastrop, TX

Work

Company: We logo anything Jan 2012 Position: Company owner

Education

Degree: Bachelors, Bachelor of Science School / High School: Sam Houston State University 1978 to 1981 Specialities: Physics

Skills

Semiconductors • Spc • Manufacturing • Jmp • Engineering Management • Design of Experiments • Metrology • Photolithography • Troubleshooting • Ic • Six Sigma • Electrical Engineering • Mig Welding

Industries

Printing

Resumes

Resumes

Terri Couteau Photo 1

Company Owner

View page
Location:
331 La Reata Trl, Smithville, TX 78957
Industry:
Printing
Work:
We Logo Anything
Company Owner

Spansion Apr 2004 - Jan 2012
Senior Member of Technical Staff

Fishhead Press Apr 2004 - Jan 2012
Editor and Technical Writer

Hill Country Flyfishers Apr 2004 - Jan 2012
Equipment Manager and Guide

Amd Feb 1998 - Apr 2004
Member Technical Staff
Education:
Sam Houston State University 1978 - 1981
Bachelors, Bachelor of Science, Physics
Texas A&M University 1976 - 1980
Skills:
Semiconductors
Spc
Manufacturing
Jmp
Engineering Management
Design of Experiments
Metrology
Photolithography
Troubleshooting
Ic
Six Sigma
Electrical Engineering
Mig Welding

Business Records

Name / Title
Company / Classification
Phones & Addresses
Terri A. Couteau
President
Advance Embroidery & Promotions
Commercial Printing
331 Ln Reata Trl, Flatonia, TX 78957
Terri A Couteau
President
WIND KNOT INCORPORATED
331 Ln Reata Trl, Smithville, TX 78957
Terri A. Couteau
Principal
Fabric Interiors
Business Services
331 Ln Reata Trl, Flatonia, TX 78957

Publications

Us Patents

System And Method For Controlling Polysilicon Feature Critical Dimension During Processing

View page
US Patent:
6348289, Feb 19, 2002
Filed:
Aug 3, 1999
Appl. No.:
09/366486
Inventors:
Terri A. Couteau - Rosanky TX
W. Jarrett Campbell - Austin TX
Anthony Toprac - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G03F 730
US Classification:
430 30, 438 17
Abstract:
A method for processing a semiconductor topography is presented. In the present processing method, a semiconductor topography may be provided having a polysilicon feature arranged above a semiconductor substrate. The polysilicon feature may have an initial polysilicon feature critical dimension (CD). A chemical mixture, preferably contained in a chemical vessel, may also be provided. A polysilicon etch rate-effective attribute of the chemical mixture may be measured. Subsequently, an exposure time to the chemical mixture for the semiconductor topography may be calculated from the polysilicon etch rate-effective attribute, the initial polysilicon feature CD, and a goal polysilicon feature CD. By calculating an exposure time for the semiconductor topography in such a manner, the method preferably allows a final polysilicon feature CD to be more accurately controlled than in conventional processes.

Method Of Controlling Feature Dimensions Based Upon Etch Chemistry Concentrations

View page
US Patent:
6352867, Mar 5, 2002
Filed:
Jan 5, 2000
Appl. No.:
09/478181
Inventors:
Terri A. Couteau - Rosanky TX
William Jarrett Campbell - Austin TX
Anthony J. Toprac - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Austin TX
International Classification:
H01L 2100
US Classification:
438 8, 438 7, 438 17, 438 18
Abstract:
The present invention is directed to a method of controlling the width of a gate electrode based upon the etch rate of a chemical bath. In one illustrative embodiment, the method comprises determining an etching rate for a chemical bath, determining the manufactured width of the gate electrode, and varying the time duration of an etching process performed in the bath depending upon the etch rate of the bath and the width of the gate electrode.

Method Of Detecting Crystalline Defects Using Sound Waves

View page
US Patent:
6566886, May 20, 2003
Filed:
Mar 28, 2001
Appl. No.:
09/819785
Inventors:
Terri A. Couteau - Rosanky TX
Michael J. Satterfield - Round Rock TX
Laura A. Pressley - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G01R 3108
US Classification:
324514, 73579
Abstract:
Various methods of inspecting circuit structures are provided. In one aspect, a method of detecting structural defects in a circuit structure is provided. A natural frequency of the circuit structure is determined and the circuit structure is immersed in a liquid. A first plurality of sonic pulses is sent through the liquid. The first plurality of sonic pulses have a first frequency range selected to produce a plurality of collapsing bubbles proximate the circuit structure. The collapsing bubbles produce a second plurality of sonic pulses that have a second frequency range near or including the natural frequency of the circuit structure whereby the second plurality of sonic pulses causes the circuit structure to resonate. Thereafter, the circuit structure is inspected for structural damage. Early identification of crystalline defects is facilitated.

Sacrificial Films To Provide Structural Integrity To Critical Dimension Structures

View page
US Patent:
20020142594, Oct 3, 2002
Filed:
Mar 28, 2001
Appl. No.:
09/819914
Inventors:
Terri Couteau - Rosanky TX, US
Michael Satterfield - Round Rock TX, US
Laura Pressley - Austin TX, US
Bruce Pickelsimer - McKinney TX, US
Assignee:
Advanced Micro Devices, Inc.
International Classification:
H01L021/302
H01L021/461
US Classification:
438/689000
Abstract:
Various methods of processing a circuit structure with a protective coating are provided. In one aspect, a method of processing a semiconductor substrate is provided that includes patterning a structure on the substrate and forming a protective coating on the patterned structure while leaving other surfaces on the substrate exposed. The exposed surfaces are cleaned by immersing the substrate in a liquid and subjecting the exposed surfaces to sonic pulses whereby the protective coating increases the strength of the patterned structure to reduce the potential for structural failure induced by the sonic pulses. The protective coating is then removed.

Method And Apparatus For Partial Drain During A Nitride Strip Process Step

View page
US Patent:
63263130, Dec 4, 2001
Filed:
Apr 21, 1999
Appl. No.:
9/295941
Inventors:
Terri A. Couteau - Rosanky TX
Stacie Y. Brown - Paige TX
Assignee:
Advanced Micro Devices - Sunnyvale CA
International Classification:
H01L 21302
H01L 21461
US Classification:
438745
Abstract:
A method of performing a nitride strip process step for a plurality of semiconductor wafers includes partially draining the chemical solution within a chemical bath after every nitride strip in which the oxide etch rate is within a specified range. If the oxide etch rate is above the specified range, the partial drain is performed. Once the etch rate falls within the range, the partial drain is performed every time a bath increment signal is received. If the etch rate falls below the specified range, then the bath is completely drained so that the solution may be replaced with fresh chemicals. While it is generally desirable to minimize the amount of field oxide that is removed during the nitride strip process step, the field oxide etch should be maintained at a specified level because, when below that level, the chemical solution silicon content is too high risking the possibility that the silicon will precipitate and cause undesirable effects including coating the wafers being stripped of nitride. The partial drain time is adjusted from a nominal rate according to measured oxide etch rates. For a first bath in a sequential series of baths, the nominal partial drain time is fifteen seconds.
Terri Ann Couteau from Bull Shoals, AR, age ~66 Get Report