Tedd K Stickel

47630213, Aug 9, 1988

Jul 6, 1987

7/069736

Tedd K. Stickel - Chalfont PA

Unisys Corporation - Blue Bell PA

H03K 17094

307475

A CMOS buffer receiver is provided for converting TTL or CMOS input voltage signals to CMOS signals so as to drive CMOS loads on VSLI chips. The buffer receiver comprises a reference voltage generator coupled to a compensation network having an output signal which varies with process, temperature and voltage supply. The compensated output signal is coupled to the gates of any number of current source load transistors of a plurality of series connected transistor pairs which comprise individual stabilized input converters all of which have their switchpoint located in the middle of their characteristic curves so that their switchpoints are immune to process, temperature and supply voltage variations.

44108150, Oct 18, 1983

Sep 24, 1981

6/305320

Stephen A. Ransom - Huntington Valley PA
Tedd K. Stickel - Chalfont PA
Joseph B. Tomei - Chalfont PA

Sperry Corporation - New York NY

H03K 19092

307475

A high speed gallium arsenide (GaAs) integrated circuit is provided which converts GaAs input or source signals to voltage levels for directly driving emitter coupled logic (ECL) circuits. The high speed GaAs level converter comprises a level shifting network at the input, two stages of differential amplification and a novel source follower output stage.

44940165, Jan 15, 1985

Jul 26, 1982

6/401484

Stephen A. Ransom - Huntingdon Valley PA
Tedd K. Stickel - Chalfont PA

Sperry Corporation - New York NY

H03K 19017
H03K 19094
H03K 1920

307450

A gallium arsenide buffer amplifier for use in a very large scale integrated circuits is provided. The transistor device in the buffer amplifier has a uniform depth N+ source, gate and drain region and the N+ dopant concentration is made very high which effectively reduces the resistance of the transistor device and permits the area of the device to be reduced by more than one order of magnitude while maintaining high current and power levels.

45903930, May 20, 1986

Jun 13, 1983

6/503944

Stephen A. Ransom - Huntingdon Valley PA
Tedd K. Stickel - Chalfont PA

Sperry Corporation - Blue Bell PA

H03K 1921
H03K 19094

307471

A novel high speed gallium arsenide depletion mode field effect transistor logic circuit is provided. One logic input is connected to the source electrode of the switching transistor and draws current when a low level input voltage is provided. Other logic inputs are connected to the gate electrode of the switching transistor and supplies current when a high or low level input voltage is provided. The novel logic output from the source electrode of the switching transistor is a complex OR function which may be employed for a logic family having fewer stages of logic than prior art gallium arsenide circuits.

42086396, Jun 17, 1980

Jun 16, 1978

5/916224

Tedd Stickel - Chalfont PA

Solid State Scientific Inc. - Montgomeryville PA

H03B 536

331116FE

A crystal controlled oscillator has a substantially stable frequency in an environment of wide power supply potential changes. A first CMOS device of a pair is coupled to a crystal network and operates as a substantially small signal linear amplifier. A second CMOS device of the pair forms a constant current source for the first device by means of a plurality of diodes coupled in series circuit between two terminals of the second device to produce a substantially constant biasing potential for the second device only when the potential of the power supply exceeds the value of the diode drop potentials. In this manner, the voltage across the oscillator is relatively independent of power supply voltage changes to provide frequency stability over those changes.

41048601, Aug 8, 1978

Dec 27, 1976

5/754428

Tedd Stickel - Chalfont PA

Solid State Scientific Inc. - Montgomeryville PA

G04C 300
H03K 2330
H03K 3353

58 23R

A high speed dynamic CMOS flip-flop system having a master and a slave section each of which have a different total propagation delay. Asymmetrical clock signals are applied to the master and slave sections with one cycle portion of each clock signal turning on the master section and the other cycle turning on the slave section. Each cycle portion has a time duration substantially equal to the total propagation delay of its respective master and slave section. In this manner, the duty cycle of the clock signal cycle is matched to the ratio of the propagation delays of the master and slave sections.

43933157, Jul 12, 1983

May 18, 1981

6/264898

Tedd K. Stickel - Chalfont PA
Stephen A. Ransom - Huntingdon Valley PA

Sperry Corporation - New York NY

H03K 500
H03K 19092

307264

This invention provides a novel high-gain stabilized converter circuit which is adapted to convert emitter coupled logic (ECL) signals for use in gallium arsenide (Ga As) circuits. The novel converter is adapted to be made in gallium arsenide logic on the same chip as the logic circuitry which it is driving. The converter includes a novel differential amplifier having a level shifting network at the active input and a second level shifting network at the reference input to provide a stabilized high-gain circuit which is compensated for variations in temperature and process deviations.

44044801, Sep 13, 1983

Feb 1, 1982

6/344585

Stephen A. Ransom - Huntingdon Valley PA
Tedd K. Stickel - Chalfont PA

Sperry Corporation - New York NY

H03K 19094
H03K 19017
H03K 1920

307475

The present invention provides a high-speed low-power gallium arsenide basic logic circuit which is capable of being driven by either emitter coupled logic or gallium arsenide logic level signals to provide combinational logic gating such as OR-AND, OR-NAND, OR-AND-OR and OR-AND-NOR capable of driving directly either emitter coupled logic or gallium arsenide logic circuits. The combinational logic gating is basically accomplished by diode logic which performs other functions and which requires less area on an integrated circuit chip than active switching transistors.