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Swaroop Ghosh

from State College, PA
Age ~45
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Related to:
Subhra S GhoshDebjyoti Ghosh, 47
Connected to:
Ajay C Ghosh, 40Alok K Ghosh, 51Ananda K Ghosh, 44Anwesha Ghosh, 28Aradhana Ghosh, 49Ashok Ghosh, 59Atindra N Ghosh, 52Avignan Ghosh, 44Bijan K Ghosh, 58Biswanath Ghosh, 46

Swaroop Ghosh Phones & Addresses

  • 1905 Autumnwood Dr, State College, PA 16801
  • Tampa, FL
  • Hillsboro, OR
  • West Lafayette, IN
  • Chandler, AZ
  • W Lafayette, IN
  • Cincinnati, OH

Resumes

Resumes

Swaroop Ghosh Photo 1

Associate Professor

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Location:
State College, PA
Industry:
Higher Education
Work:
Penn State University
Associate Professor
University of South Florida Aug 2012 - Aug 2016
Assistant Professor
Intel Corporation Sep 2008 - Jul 2012
Senior Research and Development Engineer
Amd 2007 - 2007
Intern In Memory Design Group
Intel Corporation May 2006 - Aug 2006
Intern In Memory Test Group
Education:
Purdue University 2004 - 2008
Doctorates, Doctor of Philosophy, Computer Engineering University of Cincinnati 2002 - 2004
Master of Science, Masters, Computer Engineering Doms, Iit Roorkee 1996 - 2000
Bachelor of Engineering, Bachelors, Electrical Engineering
Skills:
Research
Development
Intel
Swaroop Ghosh Photo 2

Swaroop Ghosh

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Publications

Us Patents

Nand Logic Word Line Selection

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US Patent:
8456946, Jun 4, 2013
Filed:
Dec 22, 2010
Appl. No.:
12/928949
Inventors:
Swaroop Ghosh - Hillsboro OR, US
Dinesh Somasekhar - Portland OR, US
Balaji Srinivasan - Hillsboro OR, US
Fatih Hamzaoglu - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 8/00
US Classification:
36523006, 36518905, 36518908
Abstract:
A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.

Nor Logic Word Line Selection

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US Patent:
8547777, Oct 1, 2013
Filed:
Dec 22, 2010
Appl. No.:
12/928989
Inventors:
Swaroop Ghosh - Hillsboro OR, US
Dinesh Somasekhar - Portland OR, US
Balaji Srinivasan - Hillsboro OR, US
Fatih Hamzaoglu - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 8/08
G11C 8/10
G11C 8/02
US Classification:
36523006, 36518908, 36523002
Abstract:
A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.

Hierarchical Dram Sensing

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US Patent:
8406073, Mar 26, 2013
Filed:
Dec 22, 2010
Appl. No.:
12/928948
Inventors:
Dinesh Somasekhar - Portland OR, US
Gunjan Pandya - Portland OR, US
Kevin Zhang - Portland OR, US
Fatih Hamzaoglu - Portland OR, US
Balaji Srinivasan - Hillsboro OR, US
Swaroop Ghosh - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 8/00
US Classification:
365203, 36523003
Abstract:
A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.

Aging-Sensitive Recycling Sensors For Chip Authentication

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US Patent:
20190018058, Jan 17, 2019
Filed:
Sep 19, 2018
Appl. No.:
16/135445
Inventors:
Swaroop Ghosh - Tampa FL, US
Cheng-Wei Lin - Seffner FL, US
Assignee:
University of South Florida - Tampa FL
International Classification:
G01R 31/28
G01R 23/02
Abstract:
Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

Threshold Voltage Defined Switches For Programmable Camouflage Gates

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US Patent:
20180302095, Oct 18, 2018
Filed:
Jun 19, 2018
Appl. No.:
16/011977
Inventors:
Anirudh Srikant Iyengar - Tampa FL, US
Swaroop Ghosh - Tampa FL, US
Deepakreddy Vontela - Tampa FL, US
Assignee:
University of South Florida - Tampa FL
International Classification:
H03K 19/177
G06F 17/50
H03K 17/30
G06F 21/75
H01L 23/00
Abstract:
Disclosed are various embodiments providing circuitry that includes camouflaged gates that each have multiple switches arranged in a predefined format. A switch at a specific position in one camouflaged gate can have a different threshold voltage than a switch at the specific position in another camouflaged gate. The logical function performed by the camouflaged gate can be based on which of the switches have a low threshold voltage and which of the switches have a high threshold voltage.

Wide Operating Level Shifters

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US Patent:
20170237439, Aug 17, 2017
Filed:
May 4, 2017
Appl. No.:
15/586888
Inventors:
Swaroop Ghosh - Tampa FL, US
Kenneth Ramclam - Port Charlotte FL, US
Assignee:
University of South Florida - Tampa FL
International Classification:
H03K 19/0185
G11C 11/4094
G11C 11/408
Abstract:
Aspects of wide operating range level shifter designs are described. One embodiment includes a level shifter configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, a pulse generator configured to generate a pulse in response to sensing a rise transition on the input signal, and a droop circuit configured to decouple at least a portion of the level shifter from the second voltage domain in response to the pulse. According to one aspect of the embodiments, the pulse can be provided to the droop circuit to decouple at least a portion of the level shifter from the second voltage domain and reduce contention between transistors in the level shifter. Using the concepts described herein, the worst case rise time delay for level shifters can be significantly reduced.

Physically Unclonable Function Based On Domain Wall Memory And Method Of Use

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US Patent:
20170062072, Mar 2, 2017
Filed:
Nov 7, 2016
Appl. No.:
15/330829
Inventors:
Swaroop Ghosh - Tampa FL, US
Anirudh Srikant Iyengar - Centre Hall PA, US
Kenneth Ramclam - Tampa FL, US
Assignee:
University of South Florida - Tampa FL
International Classification:
G11C 19/08
Abstract:
A system and method for providing a physically unclonable function (PFU) is described. In operation, the method includes applying a domain wall shift pulse challenge to a plurality of nanowires of a domain wall memory (DWM) array, wherein the nanowires of the domain wall memory (DWM) array have process induced variations, resulting in pinning potentials which affect the velocity of the domain walls along the length of the nanowires. Following the application of the domain wall shift pulse, the response to the challenge is determined by measuring the response of the plurality of nanowires of the domain wall memory to the applied domain wall shift pulse challenge to provide a physically unclonable function (PUF) for the integrated circuit.

Mtj-Based Content Addressable Memory

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US Patent:
20170018308, Jan 19, 2017
Filed:
Jul 8, 2016
Appl. No.:
15/205813
Inventors:
Swaroop Ghosh - Tampa FL, US
Cheng Wei Lin - Seffner FL, US
Assignee:
UNIVERSITY OF SOUTH FLORIDA - TAMPA FL
International Classification:
G11C 15/04
G11C 11/16
Abstract:
Embodiments of the subject invention provide a three transistor, two domain-wall-based magnetic tunnel junction CAM cell (3T-2DW-MTJ CAM). A four transistor, two magnetic tunnel junction ternary CAM cell (4T-2MTJ TCAM) is also provided. An array of the provided CAM cells forms words of various lengths, such as 4-bit, 8-bit, and 16-bit words. Longer CAM words can be formed by an array having hierarchical structures of CAM cells having smaller word sizes, such as 4-bit words or 8-bit words.
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Swaroop Ghosh from State College, PA, age ~45 Get Report