Swarnal Borthakur

7560371, Jul 14, 2009

Aug 29, 2006

11/511619

Ross S. Dando - Nampa ID, US
Steven Oliver - Boise ID, US
Swarnal Borthakur - Boise ID, US
Kevin Hutto - Kuna ID, US

Micron Technology, Inc. - Boise ID

H01L 21/20

438612, 438613, 438614, 438108, 438113, 257E23075, 257E23067, 257E23174

Methods of forming a conductive via in a substrate include contacting the substrate with a wave of conductive liquid material, such as molten solder, and drawing the liquid material into the aperture with a vacuum. The wave may be formed by flowing the liquid material out from an outlet in a direction generally against the gravitational field. The liquid material may be solidified to form an electrically conductive structure. A plurality of apertures may be selectively filled with the liquid material one at a time, and liquids having different compositions may be used to provide conductive vias having different compositions in the same substrate. Systems for forming conductive vias include a substrate fixture, a vacuum device having a vacuum fixture, and a solder-dispensing device configured to provide a wave of molten solder material. Relative lateral and vertical movement is provided between the wave of molten solder and a substrate supported by the substrate fixture.

7629249, Dec 8, 2009

Aug 28, 2006

11/511690

Swarnal Borthakur - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 21/4763

438637, 438687, 257E21584, 257E21585, 257E21591

Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance with one embodiment includes disposing a conductive lining on walls of a via in a microfeature workpiece, so that a space is located between opposing portions of the lining facing toward each other from opposing portions of the wall. The method can further include chemically reacting the lining with a reactive material to form a chemical compound from a constituent of the reactive material and a constituent of the lining. The method can still further include at least partially filling the space with the compound. In particular embodiments, the conductive lining includes copper, the reactive material includes sulfur hexafluoride, and the chemical compound that at least partially fills the space in the via includes copper sulfide.

7767544, Aug 3, 2010

Apr 12, 2007

11/786609

Swarnal Borthakur - Boise ID, US

Micron Technology Inc. - Boise ID

H01L 21/30
H01L 21/46
H01L 21/50
H01L 21/48
H01L 21/44

438456, 438455, 438106

Embodiments of the present invention are generally directed to a method for manufacturing a semiconductor device. In one embodiment, the method includes providing a substrate that includes a via or interconnect. In this embodiment, the method also includes forming a sealed array, in which forming such an array includes attaching a carrier to a first surface of the substrate to form a sealed cavity between the carrier and the substrate. Further, the method of this embodiment also includes forming a redistribution layer on the sealed array over a second surface of the substrate. Devices and systems having a carrier attached to a substrate are also disclosed.

7947601, May 24, 2011

Mar 24, 2009

12/410343

Swarnal Borthakur - Boise ID, US
Marc Sulfridge - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 21/00

438669, 438456, 438 73

Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. The method can comprise covering the electrical connectors with a radiation blocking layer and forming apertures aligned with the electrical connectors through a layer of photo-resist on the radiation blocking layer. The radiation blocking layer is not photoreactive such that it cannot be patterned using radiation. The method further includes etching openings in the radiation blocking layer through the apertures of the photo-resist layer.

7968962, Jun 28, 2011

Aug 2, 2010

12/848786

Swarnal Borthakur - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 31/0203
H01L 31/00
H01L 31/0232
H01L 23/52
H01L 23/48

257433, 257431, 257432, 257434, 257774, 257E31127

A semiconductor device is disclosed. In one embodiment, a device includes a substrate having one or more vias and a carrier coupled to the substrate to form a sealed cavity between the carrier and the substrate. In some embodiments, the sealed cavity may be pressurized. The device may also include a redistribution layer formed over the one or more vias on a side of the substrate. Other devices, systems, and methods are also disclosed.

7973411, Jul 5, 2011

Nov 23, 2009

12/624215

Swarnal Borthakur - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 23/48

257762, 257E23141

Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance with one embodiment includes disposing a conductive lining on walls of a via in a microfeature workpiece, so that a space is located between opposing portions of the lining facing toward each other from opposing portions of the wall. The method can further include chemically reacting the lining with a reactive material to form a chemical compound from a constituent of the reactive material and a constituent of the lining. The method can still further include at least partially filling the space with the compound. In particular embodiments, the conductive lining includes copper, the reactive material includes sulfur hexafluoride, and the chemical compound that at least partially fills the space in the via includes copper sulfide.

7989266, Aug 2, 2011

Jun 18, 2009

12/487547

Swarnal Borthakur - Boise ID, US
Andy Perkins - Boise ID, US
Rick Lake - Meridian ID, US
Marc Sulfridge - Boise ID, US

Aptina Imaging Corporation - George Town

H01L 21/00

438110, 438 63, 438458, 257E21499, 257E21599

A wafer of integrated circuits may be bonded to a carrier wafer using a layer of bonding material. The thickness of the wafer of integrated circuits may then be reduced using a series of grinding operations. After grinding, backside processing operations may be performed to form scribe channels that separate the die from each other and to form through-wafer vias. The scribe channels may be formed by dry etching and may have rectangular shapes, circular shapes, or other shapes. A pick and place tool may have a heated head. The bonding layer material may be based on a thermoplastic or other material that can be released by application of heat by the heated head of the pick and place tool. The pick and place tool may individually debond each of the integrated circuits from the carrier wafer and may mount the debonded circuits in packages.

8048708, Nov 1, 2011

Jun 25, 2008

12/213836

Swarnal Borthakur - Boise ID, US
Rick Lake - Meridian ID, US
Andy Perkins - Boise ID, US
Scott Churchwell - Boise ID, US
Steve Oliver - San Jose CA, US

Micron Technology, Inc. - Boise ID

H01L 21/00

438 64, 257433, 257E21499

Method and apparatus providing a wafer level fabrication of imager modules in which a permanent carrier protects imager devices on an imager wafer and is used to support a lens wafer.