Search

Steven J Urish

from Raleigh, NC
Age ~53
Get Report
Related to:
Mark M Urish, 52Mark UrishJane L Urish, 81
Connected to:
Carmen D Urish, 47Heidi H Urish, 54Jay T Urish, 47Charles Urishko, 109Melissa Urishko, 41Javier Urista, 62Nelly D Urista, 73Sabrina R Urista, 42Talia Urista, 31Oscar Urita, 31

Steven Urish Phones & Addresses

  • 2630 Fairview Rd, Raleigh, NC 27608 (919) 803-6186
  • 110 Prospect St, Burl, VT 05401 (802) 864-3527
  • Burlington, VT
  • Lima, OH
  • Winooski, VT

Work

Position: Professional/Technical

Education

Degree: Associate degree or higher

Interests

job inquiries, expertise requests, busin...

Industries

Semiconductors

Resumes

Resumes

Steven Urish Photo 1

Design Engineer At Ibm

View page
Location:
Burlington, Vermont Area
Industry:
Semiconductors
Experience:
IBM (Public Company; 10,001 or more employees; IBM; Information Technology and Services industry): Design Engineer,  (-) 

Publications

Us Patents

Method And Apparatus For Efficient Utilization Of Electronic Fuse Source Connections

View page
US Patent:
7082065, Jul 25, 2006
Filed:
Sep 17, 2004
Appl. No.:
10/711430
Inventors:
David James Hathaway - Underhill VT, US
Steven Joseph Urish - Burlington VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 29/00
US Classification:
365200, 3652257
Abstract:
A method for and an apparatus in which the FSOURCE connection in a fuse domain is split into multiple nets, allowing flexible placement of primary fuses in the floorplan, is provided. In particular, multiple FSOURCE connections (e. g. C4 pads or wire pads) are provided in the floorplan, allowing flexible placement of primary fuses without additional overhead.

Method And Apparatus For Depopulating Peripheral Input/Output Cells

View page
US Patent:
7194707, Mar 20, 2007
Filed:
Sep 17, 2004
Appl. No.:
10/711431
Inventors:
Douglas W. Stout - Milton VT, US
Steven J. Urish - Burlington VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 4, 716 12
Abstract:
Chip area corresponding to unnecessary I/O cell sites is recovered and made usable for additional core cells and power connections by grouping I/O cells into I/O kernels of contiguous I/O cells having power connections independent of other I/O kernels and depopulating I/O cell sites in accordance with areas corresponding to I/O kernels. Since I/O kernels have dedicated power connections, no power busses are present in the depopulated I/O cell sites which can then be freely use for additional core cells, power connections or the like. This technique also allows selection of a chip of minimum required area to be determined prior to design of chip layout.

Method And System Of Modifying Integrated Circuit Power Rails

View page
US Patent:
20020170020, Nov 14, 2002
Filed:
May 10, 2001
Appl. No.:
09/853115
Inventors:
Laura Darden - Essex Junction VT, US
Scott Gould - South Burlington VT, US
Patrick Ryan - Essex Junction VT, US
Steven Urish - Burlington VT, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F017/50
US Classification:
716/002000
Abstract:
A method and system for modifying power rails of an integrated circuit having improved wireability. This is accomplished by initially generating a power railing design of the integrated circuit into a three-dimensional rail based model. Next, analysis of the design is performed as to placement of the power rails in relation to neighboring elements that affects a predefined wireability. Finally, modification of a segment of each power rail that affects wireability is performed so that required power supply to the neighboring elements (e.g., pins, rails etc.) remains unaffected.

Data Pipeline Circuit Supporting Increased Data Transfer Interface Frequency With Reduced Power Consumption, And Related Methods

View page
US Patent:
20220197646, Jun 23, 2022
Filed:
Dec 21, 2020
Appl. No.:
17/129187
Inventors:
- Redwood WA, US
Steven J. Urish - Raleigh NC, US
International Classification:
G06F 9/30
G06F 9/38
G06F 1/08
G06F 13/12
Abstract:
A data pipeline circuit includes an upstream interface circuit that receives sequential data and a downstream interface circuit that transfers the sequential data to a downstream circuit. A ready signal indicates the downstream circuit is ready to receive the sequential data. The data pipeline circuit includes a first data latch, a second data latch and a first status latch. The first data latch receives the sequential data. The first status latch generates an available signal that is asserted to indicate the second data latch is available to receive the sequential data. The second data latch receives the sequential data in response on the available signal being asserted and the ready signal indicating the downstream circuit is not ready to receive the sequential data on the data output. Limiting conditions in which the sequential data is stored in the second data latch significantly reduces power consumption of the data pipeline circuit.

Verifying Partial Good Voltage Island Structures

View page
US Patent:
20150070048, Mar 12, 2015
Filed:
Sep 6, 2013
Appl. No.:
14/019957
Inventors:
- Armonk NY, US
Steven F. OAKLAND - Colchester VT, US
Michael R. OUELLETTE - Westford VT, US
Steven J. URISH - Burlington VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 19/003
G06F 17/50
US Classification:
326 10, 716104
Abstract:
Structures, methods, and systems for designing and verifying integrated circuits including redundant logic blocks are provided. An integrated circuit includes selection logic and selectable logic blocks that are individually controllable by the selection logic. The selectable logic blocks include respective instances of a redundant logic block, and respective instances of an interface logic block that selectively disable the redundant logic blocks in the integrated circuit.
Control profile
Steven J Urish from Raleigh, NC, age ~53 Get Report