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Steven Paul Pekarich

from Rowlett, TX
Age ~78
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Also known as:
Steven P Pekarich, Steven H
Connected to:
Daniel R Pekarik, 66William J Pekarik, 59Joseph H Pekarovic, 59Brett T Pekarski, 42Cory M Pekarski, 38Joyce A Pekarsky, 72Steven W Pekarthy, 84Robyn J Pekas, 61Scott J Pekas, 54Asli Pekcan, 27

Steven Pekarich Phones & Addresses

  • Rowlett, TX
  • Dallas, TX
  • 9161 Loop Rd, Slatington, PA 18080
  • Freehold, NJ
  • New Tripoli, PA

Professional Records

License Records

Steven Paul Pekarich

Address:
7309 Meadowwood Dr, Rowlett, TX 75089
License #:
A1469755
Category:
Airmen

Publications

Us Patents

Address Generator For Interleaving Data

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US Patent:
6549998, Apr 15, 2003
Filed:
Jan 14, 2000
Appl. No.:
09/483574
Inventors:
Steven P. Pekarich - Slatington PA
Xiao-An Wang - Allentown PA
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G06F 1202
US Classification:
711220, 711211, 370320
Abstract:
An interleaver generates a valid interleaved data address for each iteration i of the mapping by the interleaver without employing a multiplication operation. The interleaver includes an address generator comprises two counters, bit-reverse and index tables, and an accumulation register array. The interleaver further comprises two adders, two registers storing tentative address values address and address , and select logic including a comparator, two buffers, and a multiplexer (mux). Two counters are employed to allow the interleaver to generate at least one valid address for each iteration, and a tentative address is generated from each output value of the two counters. Each iteration generates an output interleaved address. A tentative address is generated by using a portion of the counter value as an address to select a corresponding entry from each of the bit-reverse and index tables and the accumulation register array. The selected values from the index table and accumulation register array are combined in an adder.

Limiting Range Of Extrinsic Information For Iterative Decoding

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US Patent:
6614858, Sep 2, 2003
Filed:
Feb 17, 2000
Appl. No.:
09/506019
Inventors:
Steven P. Pekarich - Slatington PA
Xiao-An Wang - Allentown PA
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03D 100
US Classification:
375340, 375341, 714795
Abstract:
An iterative decoder limits the range of extrinsic information used for iterative decoding of an encoded frame of data. The iterative decoder includes two or more separate decoders for decoding a received encoded frame of data. Each decoder employs extrinsic information generated from the soft data generated by another decoder decoding the encoded frame of data. The extrinsic information includes an approximate measure of the probability that a particular transmitted bit received by the iterative decoder is a logic 0 or logic 1. The extrinsic information for the bit originates with one decoder and is used by another decoder as external information about that bit. Implementations of the iterative decoder use saturation values to define the boundaries of the range. The saturation values are selected such that either no or relatively small degradation in BER occurs, and the saturation values also define the width of the binary representation of the extrinsic information.

Trellis Transition-Probability Calculation With Threshold Normalization

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US Patent:
6633615, Oct 14, 2003
Filed:
Jan 31, 2000
Appl. No.:
09/495161
Inventors:
Steven P. Pekarich - Slatington PA
Xiao-An Wang - Allentown PA
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04L 512
US Classification:
375265, 375259, 375260, 375261, 375262, 375341, 714752, 714755, 714760, 714796
Abstract:
A circuit performs threshold normalization of accumulated transition probabilities for a given state of a state transition trellis in a maximum likelihood detector. Threshold normalization may be accomplished by comparison and setting of a single bit in stored transition probabilities. Threshold value comparison may be accomplished by comparing the b bit of the stored transition probabilities if the threshold value is b. When all transition probabilities exceed the threshold value at a stage of the trellis, the transition probabilities are scaled, such as by subtracting the threshold value. Scaling may be implemented by setting the compared b bits to zero before storage. In general, since accumulated transition probabilities are monotonically increasing for transition probabilities of paths through the trellis in both forward and reverse directions, the present invention may be employed for both threshold normalization of both the forward () and reverse () transition probabilities.

Reconfigurable Chip Level Equalizer Architecture For Multiple Antenna Systems

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US Patent:
7561618, Jul 14, 2009
Filed:
Apr 14, 2005
Appl. No.:
11/105755
Inventors:
Steven P. Pekarich - Rowlett TX, US
Timothy M. Schmidl - Dallas TX, US
Aris Papasakellariou - Dallas TX, US
Anand G. Dabak - Plano TX, US
Eko N. Onggosanusi - Allen TX, US
Manish Goel - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03H 7/30
US Classification:
375232
Abstract:
A system comprising a plurality of adaptive equalizers adapted to couple to a plurality of receive antennas, each of the antennas capable of receiving a multipath delay profile estimate (MDPE), control logic interconnecting at least some of the adaptive equalizers, and a control mechanism that, according to different MDPEs, configures at least some of the adaptive equalizers and control logic.

Reconfigurable Chip Level Equalizer Architecture

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US Patent:
8135057, Mar 13, 2012
Filed:
Nov 3, 2003
Appl. No.:
10/699707
Inventors:
Steven P. Pekarich - Rowlett TX, US
Timothy M. Schmidl - Dallas TX, US
Gibong Jeong - San Diego CA, US
Aris Papasakellariou - Dallas TX, US
Anand G. Dabak - Plano TX, US
Eko N. Onggosanusi - Allen TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03H 7/30
US Classification:
375232, 375230, 375231, 375233, 375229, 375347, 375234, 375316, 375349
Abstract:
A reconfigurable chip level equalizer having circuitry that restores signal orthogonality and eliminates channel interference for a wireless transmitted signal. In at least some embodiments, the reconfigurable chip level equalizer comprises two or more adaptive equalizers, a plurality of operational blocks that interconnect the two or more adaptive equalizers, and a control mechanism that configures the two or more adaptive equalizers and operational blocks according to different signal delay profiles.

Integrated Circuit Multi-Level Interconnection Technique

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US Patent:
56636776, Sep 2, 1997
Filed:
Mar 30, 1995
Appl. No.:
8/413527
Inventors:
Ronald Lamar Freyman - Bethlehem PA
Ted R. Martin - Allentown PA
Steven Paul Pekarich - Slatington PA
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H01L 2500
US Classification:
327565
Abstract:
An improved integrated circuit conductor layout technique provides lower and upper conductor levels that bound circuit blocks and provide for power supply voltage distribution to the circuitry in the circuit blocks. The lower and upper conductor levels also provide for first and second groups of parallel signal conductors in wiring channels between circuit blocks. An intermediate conductor level is located between the lower and upper conductor levels, and conducts power supply voltages between adjacent circuit blocks. The power supply conductors formed in the intermediate conductor level also serve to isolate the signal conductors in the lower conductor level from the signal conductors in the upper conductor level (and vice-versa) in the wiring channel. This isolation typically improves the design of the integrated circuit by providing more reliable estimates of signal propagation in the wiring channels.

Microprocessor Having Decision Pointer To Process Restore Position

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US Patent:
45625387, Dec 31, 1985
Filed:
May 16, 1983
Appl. No.:
6/494776
Inventors:
Alan D. Berenbaum - Summit NJ
Anand Jagannathan - Hopkinton MA
John J. Molinelli - Fair Haven NJ
Steven P. Pekarich - Eatontown NJ
Assignee:
AT&T Bell Laboratories - Murray Hill NJ
International Classification:
G06F 900
US Classification:
364200
Abstract:
Process switch operations common in multiprogramming environments in commercially available data processors, are carried out faster by providing a decision-making capability for determining whether it is later to be restored at the beginning of the process or at the point of interruption. Both hardware and software implementations are disclosed.
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Steven Paul Pekarich from Rowlett, TX, age ~78 Get Report