Steven Michael Eustis

6570254, May 27, 2003

May 31, 2001

09/871087

John B. DeForge - Barre VT
David E. Douse - Hinesburg VT
Steven M. Eustis - Essex Junction VT
Erik L. Hedberg - Essex Junction VT
Susan M. Litten - Jericho VT
Endre P. Thoma - Colchester VT

International Business Machines Corporation - Armonk NY

H01L 2348

257758

Mask programmable conductors of the same construction as the mask layers they define are utilized for mask vintage identification. When the actual mask layer is altered, the change is recorded within the mask itself. Mask identification can be fabricated to identify the following type of mask layers: DTâdeep trench; SSâsurface strap; DIFFâDiffusion; NDIFFâN Diffusion; PDIFFâP Diffusion; WLâN wells; PCâpolysilicon gates; BNâN diffusion Implant; BPâP diffusion Implant; C âfirst contact; M âfirst metal layer; C âsecond contact; and, M2âsecond metal layer. Conducting paths that incorporate, in series, the mask programmable conductor technology devices are: M -C -PC-C -DIFF-C -M -C -M ; M -C -PDIFF-SS-DT-SS-PDIFF-C -M -C -M ; M -C -M -C -PC-C -M ; M -C -M -C -NDIFF-WL-NDIFF-C -M ; and, M -C -M -C -NDIFF-C -M -C -PC-C -M. These conducting paths are electrically opened with the omission of any of the layers in the series path.

6600673, Jul 29, 2003

Jan 31, 2003

10/248599

Peter F. Croce - Essex Junction VT
Steven M. Eustis - Essex Junction VT
Ronald A. Piro - Essex Junction VT

International Business Machines Corporation - Armonk NY

G11C 1712

365104, 365103, 365 94, 36518905

A method and structure for a pair of read only memory (ROM) cells having a first latch and a second latch connected to the first latch. The first latch and the second latch behave as master and slave latches to one another. The first latch and the second latch include a write bitline connection that is permanently connected to a fixed voltage source to permanently program the first latch and the second latch to permanent ROM values.

6675273, Jan 6, 2004

May 31, 2001

09/871057

Steven Michael Eustis - Essex Junction VT
Robert Lloyd Barry - Essex Junction VT
Peter Francis Croce - Essex Junction VT

International Business Machines Corporation - Armonk NY

G06F 1300

711167, 365194

A memory circuitry is designed to efficiently obtain a predictable array output when an invalid address is requested. The memory circuit comprises an invalid word line path in addition to the standard valid word line path. In order to provide correct output, a dummy word line output of a first decode logic is delayed and the delayed dummy word line output is ANDed with a word line output to update the data out latch. Further, the invalid word line output of a second decode logic is also delayed, and the delayed invalid word line output is ORed with the delayed dummy word line output to reset the control logic. ORing the delayed signals allows the predictable output to be provided at a same clock time, irrespective of whether a valid address or an invalid address is decoded.

6721927, Apr 13, 2004

Mar 29, 2002

10/063213

Peter F. Croce - Essex Junction VT
Steven M. Eustis - Essex Junction VT
Yabin Wang - Ithaca NY

International Business Machines Corporation - Armonk NY

G06F 1750

716 4, 716 2, 716 7, 716 8, 716 17

A method of designing an integrated circuit chip includes preparing a first macro to have a first power consumption rate, preparing a second macro to have a second power consumption rate different than the first power consumption rate, designing the circuit, measuring performance characteristics of the circuit, and substituting the second macro for the first macro to improve the performance characteristics. The first macro and the second macro have the same function, devices, surface area size, external wiring pattern, and timing characteristics.

6778419, Aug 17, 2004

Mar 29, 2002

10/063212

Robert L. Barry - Essex Junction VT
Peter F. Croce - Essex Junction VT
Steven M. Eustis - Essex Junction VT
Yabin Wang - Ithaca NY

International Business Machines Corporation - Armonk NY

G11C 1700

365 94, 365 72, 365174, 365214

A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

6922349, Jul 26, 2005

Jun 9, 2004

10/864238

Robert L. Barry - Essex Junction VT, US
Peter F. Croce - Essex Junction VT, US
Steven M. Eustis - Essex Junction VT, US
Yabin Wang - Ithaca NY, US

International Business Machines Corporation - Armonk NY

G11C017/00
G11C005/06

365 94, 365104, 365 72

A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

6928377, Aug 9, 2005

Sep 9, 2003

10/658940

Steven M. Eustis - Essex Junction VT, US
Krishnendu Mondal - Burlington VT, US
Michael R. Ouellette - Westford VT, US
Jeremy P. Rowland - Essex Junction VT, US

International Business Machines Corporation - Armonk NY

G01R031/00

702118, 702117

Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated. Once the second pass of self-test is completed, the column and unique failing row addresses are transported to the e-fuse macros and permanently stored in the chip.

6944075, Sep 13, 2005

Jan 5, 2005

10/905451

Steven M. Eustis - Essex Junction VT, US
Michael T. Fragano - Essex Junction VT, US
Michael R. Ouellette - Westford VT, US

International Business Machines Corporation - Armonk NY

G11C007/00

365200, 36523006, 711718

A method of assigning bits to redundant regions for variable bit redundancy region boundaries in a compliable memory such as a 1-port SRAM is provided. Methods include allocating bits between the redundant regions in nearly equal proportions while minimizing the amount of chip real estate consumed by the memory. Methods also includes allocating bits in equal portions between redundant regions while occupying slightly more memory chip real estate. Methods also allocate bits into redundant regions with a simplified procedure which may or may not allocate bits into the redundant regions in equal proportions. All of the methods allow the total number of memory bits in the complied memory to be re-defined while maintaining the same allocation characteristics for each method. Accordingly, the methods allow efficient use of redundant memory bits while also conserving chip real estate or offering simplified allocation steps.