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Sridhar R Tirumalai

from Chandler, AZ
Age ~41
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Also known as:
Sridha Tirumala, Sridhar I
Related to:
Vidya T Ramachandran, 40
Connected to:
Neelima Tirumalasetti, 48Reddy M Tirumala, 31Suresh K Tirumalareddy, 53Venkat R Tirumala, 48Abebe D Tiruneh, 52Nebiyu D Tiruneh, 53Saravanakumar V Tiruthani, 53Veena S Tiruvallur, 56Chandrashekar R Tiruvidula, 50Sai M Tiruvuri, 38

Sridhar Tirumalai Phones & Addresses

  • Chandler, AZ
  • Gainesville, FL
  • Phoenix, AZ
  • Dallas, TX
  • Stamps, AR

Work

Company: Intel corp. Jun 2000 Position: Analog design engineer

Education

Degree: M.S. School / High School: University of Florida 1998 to 2000 Specialities: Electrical & Computer Engineering

Skills

Signal Design • Design • Memory • Analog

Industries

Semiconductors

Resumes

Resumes

Sridhar Tirumalai Photo 1

Senior Analog Design Engineer

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Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Semiconductors
Work:
Intel Corp. since Jun 2000
Analog Design Engineer
intel 1999 - 2008
analog
Education:
University of Florida 1998 - 2000
M.S., Electrical & Computer Engineering National Institute of Technology Tiruchirappalli 1994 - 1998
B.E., Instrumentation & Control Engineering
Skills:
Signal Design
Design
Memory
Analog

Publications

Us Patents

Fast Lock Scheme For Phase Locked Loops And Delay Locked Loops

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US Patent:
20070229127, Oct 4, 2007
Filed:
Mar 31, 2006
Appl. No.:
11/396041
Inventors:
Sridhar Tirumalai - Chandler AZ, US
Amir Bashir - El Dorado Hills CA, US
Jing Li - Folsom CA, US
Andrew Volk - Granite Bay CA, US
International Classification:
H03L 7/06
US Classification:
327156000
Abstract:
A fast lock scheme for phase locked loops and delay locked loops, where an embodiment comprises a startup circuit that is enabled at the beginning of a startup mode and is disabled upon a phase transition detection in the reference and feedback signals to the phase locked loop or delay locked loop. Further embodiments enable a first charge pump when a phase transition is detected, and enable a second charge pump when the phase difference between the reference and feedback signals fall within a predetermined range. Other embodiments are described and claimed.

Duty Cycle Correction System And Low Dropout (Ldo) Regulator Based Delay-Locked Loop (Dll)

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US Patent:
20210320652, Oct 14, 2021
Filed:
Jun 24, 2021
Appl. No.:
17/357456
Inventors:
- Santa Clara CA, US
Roger Cheng - San Jose CA, US
Hari Venkatramani - San Jose CA, US
Navneet Dour - El Dorado Hills CA, US
Mozhgan Mansuri - Hillsboro OR, US
Bryan Casper - Ridgefield WA, US
Frank O'Mahony - Portland OR, US
Ganesh Balamurugan - Hillsboro OR, US
Kuan Zhou - Portland OR, US
Sridhar Tirumalai - Chandler AZ, US
Krishnamurthy Venkataramana - Folsom CA, US
Alex Thomas - El Dorado Hills CA, US
Quoc Nguyen - El Dorado Hills CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 5/156
H03L 7/081
G11C 7/22
G06F 1/08
G11C 7/10
Abstract:
An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Duty Cycle Correction System And Low Dropout (Ldo) Regulator Based Delay-Locked Loop (Dll)

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US Patent:
20200106430, Apr 2, 2020
Filed:
Sep 27, 2018
Appl. No.:
16/144949
Inventors:
- Santa Clara CA, US
Roger Cheng - San Jose CA, US
Hari Venkatramani - San Jose CA, US
Navneet Dour - El Dorado Hills CA, US
Mozhgan Mansuri - Hillsboro OR, US
Bryan Casper - Ridgefield WA, US
Frank O'Mahony - Portland OR, US
Ganesh Balamurugan - Hillsboro OR, US
Kuan Zhou - Portland OR, US
Sridhar Tirumalai - Chandler AZ, US
Krishnamurthy Venkataramana - Folsom CA, US
Alex Thomas - El Dorado Hills CA, US
Quoc Nguyen - El Dorado Hills CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 5/156
H03L 7/081
G11C 7/22
G11C 7/10
G06F 1/08
Abstract:
An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
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Sridhar R Tirumalai from Chandler, AZ, age ~41 Get Report