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Sorin S Georgescu

from Gilroy, CA
Age ~72
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Also known as:
Sorin Te Georgescu, Sorin C Georgescu, Sorin Stefan Georgeta, Georgeta Georgescu, Israel Georgescu, Sorin Georgesch, Georgescu Soris
Phone and address:
1520 Gold Finch Ct, Gilroy, CA 95020
(408) 972-0921
Related to:
Florentina NeaguA Georgescu, 70Ioana Georgescu, 46Sorin S Georgeta, 72Carmen Georgescu, 45Geta Georgescu
Connected to:
Aaron L Georges, 33Agnes Georges, 76Alain A Georges, 54Alexia L Georges, 49Angelo N Georges, 65Ann M Georgescu, 58Anne M Georges, 64Ashley N Georges, 36Ashley Georgeson, 28Bill Georgeson, 81

Sorin Georgescu Phones & Addresses

  • 1520 Gold Finch Ct, Gilroy, CA 95020 (408) 972-0921
  • Santa Clara, CA
  • 99 Park Essex Pl, San Jose, CA 95136
  • Cupertino, CA
  • Sunnyvale, CA

Work

Position: Food Preparation and Serving Related Occupations

Education

Degree: High school graduate or higher

Emails

s***[email protected]

Resumes

Resumes

Sorin Georgescu Photo 1

Director Technology Development

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Location:
1520 Gold Finch Ct, Gilroy, CA 95020
Industry:
Semiconductors
Work:
Power Integrations since May 2013
Dir Technology Development
ON Semiconductor Oct 2008 - May 2013
Sr Dir - Catalyst BU
Skills:
Development
Semiconductors
Technology
Power
Technology Development
Sorin Georgescu Photo 2

Sorin Georgescu

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Publications

Us Patents

Field Effect Transistor Structure For Driving Inductive Loads

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US Patent:
6617642, Sep 9, 2003
Filed:
Oct 17, 2000
Appl. No.:
09/690926
Inventors:
Sorin Stefan Georgescu - San Jose CA
Assignee:
Tripath Technology, Inc. - San Jose CA
International Classification:
H01L 2976
US Classification:
257335, 257339, 257343, 257471
Abstract:
The field effect transistor of the present invention includes a body diffusion region having a source diffusion region therein. The field effect transistor further includes a metal source contact adjacent the body diffusion region and the source diffusion region. The metal source contact forms a Schottky type contact with the body diffusion region.

Substrate Connection In An Integrated Power Circuit

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US Patent:
6737713, May 18, 2004
Filed:
Jul 2, 2002
Appl. No.:
10/189284
Inventors:
Sorin Stefan Georgescu - San Jose CA
Carl Sawtell - San Jose CA
Assignee:
Tripath Technology, Inc. - San Jose CA
International Classification:
H01L 2994
US Classification:
257394, 257368
Abstract:
An integrated circuit is described having a substrate, a power transistor in a first region of the subtracted, and a plurality of barrier regions of the substrate around the first region. Each barrier region includes a barrier transistor and at least one substrate connection connecting the barrier transistor to at least one floating region of the substrate adjacent the barrier region. During operation of the integrated circuit, the floating regions and the barrier transistors operate to inhibit operation of parasitic devices associated with the power transistor.

Non-Volatile Memory Integrated Circuit

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US Patent:
6989562, Jan 24, 2006
Filed:
Jun 20, 2003
Appl. No.:
10/600125
Inventors:
Sorin S. Georgescu - San Jose CA, US
Assignee:
Catalyst Semiconductor, Inc. - Sunnyvale CA
International Classification:
H01L 29/788
US Classification:
257315, 257314
Abstract:
A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell.

Digital Potentiometer With Resistor Binary Weighting Decoding

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US Patent:
7042380, May 9, 2006
Filed:
Jun 2, 2004
Appl. No.:
10/860476
Inventors:
Radu H. Iacob - Santa Clara CA, US
Sorin S. Georgescu - San Jose CA, US
Assignee:
Catalyst Semiconductor, Inc. - Sunnyvale CA
International Classification:
H03M 1/78
US Classification:
341154, 341144
Abstract:
A digital potentiometer includes a string of impedance units in series. The string includes identical first and second sets of impedance units whose individual impedance values increment by a power of two. One of a plurality of switches is coupled in parallel with each respective impedance unit. The switches that are coupled to the first set of impedance units receive logical control signals complementary to logical control signals received by the respective switches coupled to the second set of impedance units, so that for every impedance unit of the first set that is bypassed (not bypassed), the identical impedance unit of the second set is not bypassed (bypassed). The string may include only the first and second sets of impedance units, or may include at least one third impedance unit in series with the first and second sets in a multi-stage design.

Non-Volatile Cmos Reference Circuit

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US Patent:
7149123, Dec 12, 2006
Filed:
Apr 5, 2005
Appl. No.:
11/100347
Inventors:
Sorin S. Georgescu - San Jose CA, US
Ilie Marian I. Poenaru - Bucharest, RO
Assignee:
Catalyst Semiconductor, Inc. - Santa Clara CA
International Classification:
G11C 11/34
US Classification:
36518524, 36518503, 36518519, 36518901
Abstract:
A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a reference NVM transistor, wherein a first voltage is applied to the control gate of the first NVM transistor, and a reference voltage is applied to the control gate of the reference NVM transistor. The threshold voltage of a second NVM transistor is programmed while coupled in parallel with the reference NVM transistor, wherein a second voltage is applied to the control gate of the second NVM transistor, and the reference voltage is applied to the control gate of the reference NVM transistor. The first and second NVM transistors are then coupled in parallel, and a differential amplifier is used to generate a single-ended reference voltage in response to the programmed threshold voltages of the first and second NVM transistors.

Led Bias Current Control Using Adaptive Fractional Charge Pump

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US Patent:
7236046, Jun 26, 2007
Filed:
Nov 1, 2005
Appl. No.:
11/264884
Inventors:
Sorin S. Georgescu - San Jose CA, US
Anthony G. Russell - San Jose CA, US
Chris B. Bartholomeusz - Santa Clara CA, US
Assignee:
Catalyst Semiconductor, Inc. - Santa Clara CA
International Classification:
G05F 1/10
G05F 3/02
US Classification:
327536
Abstract:
A charge pump provides a multiplication factor of 4/3 by using a three-phase mode of operation. In a first mode, first and second capacitors are charged from an input voltage while a third capacitor drives the output voltage based on stored charge in the third capacitor. In a second mode, the voltage potential across the first capacitor is added to the input voltage to generate the output voltage. In a third mode, the voltage potential across the first capacitor is subtracted from the sum of the input voltage and the voltage potential across the second capacitor to generate the output voltage. Operated in this manner, the first, second, and third capacitors will provide the desired 4/3× voltage multiplication. This relatively low multiplication factor can be beneficial in applications such as white LED driver circuits, particularly where the input voltage is provided by a battery.

Precision Non-Volatile Cmos Reference Circuit

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US Patent:
7245536, Jul 17, 2007
Filed:
Feb 15, 2006
Appl. No.:
11/355394
Inventors:
Ilie Marian I. Poenaru - Bucharest, RO
Sabin A. Eftimie - Victoria, RO
Sorin S. Georgescu - San Jose CA, US
Assignee:
Catalyst Semiconductor, Inc. - Santa Clara CA
International Classification:
G11C 16/06
US Classification:
3651852, 36518909, 365226
Abstract:
A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a reference NVM transistor. During programming, the reference NVM transistor has a floating gate coupled to ground through a first set of capacitors, and coupled to a reference voltage through a second set of capacitors. The program threshold voltage of the first NVM transistor is dependent on the first and second sets of capacitors. The first and reference NVM transistors are then coupled in parallel, and a differential amplifier is used to generate a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor. Capacitors can be transferred between the first set and the second set, thereby providing precise adjustment of the single ended reference voltage.

Non-Volatile Memory Integrated Circuit

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US Patent:
7323742, Jan 29, 2008
Filed:
Oct 27, 2005
Appl. No.:
11/261510
Inventors:
Sorin S. Georgescu - San Jose CA, US
Assignee:
Catalyst Semiconductor, Inc. - Santa Clara CA
International Classification:
H01L 21/331
H01L 21/336
H01L 21/8222
US Classification:
257316, 438262
Abstract:
A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell.
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Sorin S Georgescu from Gilroy, CA, age ~72 Get Report