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Shruti Dhingra

from San Jose, CA
Age ~39
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Also known as:
Shruti Dhingara, Shruti Dhingre
Connected to:
Abhishek Dhingra, 41Anish Dhingra, 27Anurag Dhingra, 51Aruna Dhingra, 54Danny Dhingra, 44Deepak Dhingra, 46Gagandeep Dhingra, 40Kamlesh Dhingra, 72Karan Dhingra, 35Manish Dhingra, 47

Shruti Dhingra Phones & Addresses

  • San Jose, CA
  • Clarksburg, MD
  • Santa Clara, CA
  • Germantown, MD
  • Boyds, MD
  • Greenbelt, MD

Work

Company: Nvidia Mar 2012 Position: Senior hardware engineer

Education

Degree: Master of Science, Masters School / High School: University of Maryland 2006 to 2008 Specialities: Electrical Engineering, Electronics

Skills

Verilog • Asic • Vhdl • Systemverilog • Matlab • Rtl Coding • Perl • Fpga • Functional Verification • C • C++ • Simulations • Vlsi • Rtl Design • Unix • Shell Scripting • Digital Signal Processors • Signal Processing • Hardware • Digital Electronics • Ncsim • Nc Verilog • Coverage Analysis • Systemc • Lsf • Emacs • Xemacs • Clearcase • Simvision • Incisive Hal • Incisive Iccr • Verdi • Formality • Perforce

Languages

English

Industries

Computer Hardware

Resumes

Resumes

Shruti Dhingra Photo 1

Senior Hardware Engineer

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Location:
1420 Via Del Los Grande, San Jose, CA 95120
Industry:
Computer Hardware
Work:
Nvidia
Senior Hardware Engineer
Hughes Network Systems Jul 2008 - Feb 2012
Member Technical Staff - 3
University of Maryland Sep 2006 - May 2008
Graduate Assistant
Mantaro Product Development Services Jun 2007 - Aug 2007
Intern
Education:
University of Maryland 2006 - 2008
Master of Science, Masters, Electrical Engineering, Electronics Delhi College of Engineering 2002 - 2006
Bachelor of Engineering, Bachelors, Communication, Electronics Delhi Public School - R. K. Puram 1990 - 2002
Skills:
Verilog
Asic
Vhdl
Systemverilog
Matlab
Rtl Coding
Perl
Fpga
Functional Verification
C
C++
Simulations
Vlsi
Rtl Design
Unix
Shell Scripting
Digital Signal Processors
Signal Processing
Hardware
Digital Electronics
Ncsim
Nc Verilog
Coverage Analysis
Systemc
Lsf
Emacs
Xemacs
Clearcase
Simvision
Incisive Hal
Incisive Iccr
Verdi
Formality
Perforce
Languages:
English

Publications

Us Patents

Apparatus And Method For A Dual Mode Standard And Layered Belief Propagation Ldpc Decoder

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US Patent:
20130205182, Aug 8, 2013
Filed:
Feb 8, 2012
Appl. No.:
13/369038
Inventors:
Marwan Adas - Broadlands VA, US
Shruti Dhingra - Germantown MD, US
Shumin Zhang - Germantown MD, US
Assignee:
HUGHES NETWORKS SYSTEMS, LLC. - Germantown MD
International Classification:
H03M 13/05
G06F 11/10
US Classification:
714763, 714752, 714E11032, 714E11034
Abstract:
An apparatus for a dual mode low density parity check (LDPC) decoder including edge random access memory (RAM), last-in-first-out/first-in-first-out (LIFO/FIFO) RAM, channel RAM, and parallel datapath engines, where the datapath engines include a standard belief propagation decoding (SBD) datapath and a layered belief propagation decoding (LBD) datapath, where the SBD datapath includes a shifter, an accumulator, multiplexers, and a g( )_sbd calculator, and where the LBD datapath includes the shifter, the multiplexers, and a g′( )_lbd calculator.
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Shruti Dhingra from San Jose, CA, age ~39 Get Report