Search

Sharat C Prasad

from Saratoga, CA
Age ~62
Get Report
Also known as:
Sharat Chandra Prasad, Sharnutan S Prasad, Prasad Nutan Sharat, Chandra Prasad Sharat
Phone and address:
13670 Old Tree Way, Saratoga, CA 95070
(408) 872-1184
Related to:
Shreenivas B MendonNutan S Prasad, 67Ram C PrasadSatish C PrasadPiyush Prasad, 29Vinita Prasad
Connected to:
A Prasad, 53Aarthi Prasad, 44Aditya Prasad, 41Ak K Prasad, 55Akhilesh Prasad, 55Alexandra Prasad, 40Alvyn R Prasad, 38Alysha J Prasad, 27Ameeta D Prasad, 49Amrit K Prasad, 56

Sharat Prasad Phones & Addresses

  • 13670 Old Tree Way, Saratoga, CA 95070 (408) 872-1184
  • 811 Romani Ct, San Jose, CA 95125 (408) 265-7457
  • Dallas, TX
  • Santa Clara, CA
  • Plano, TX
  • 13670 Old Tree Way, Saratoga, CA 95070 (619) 572-0330

Work

Company: Google Position: Software engineer

Education

Degree: PhD School / High School: The University of Texas at Dallas 1996 to 2005 Specialities: Electrical Engineering

Awards

1 Book • 5+ Journal Publications • 10+ Conference Publications • 25+ Patents

Industries

Internet

Resumes

Resumes

Sharat Prasad Photo 1

Software Engineer At Google

View page
Position:
Software Engineer at Google
Location:
San Francisco Bay Area
Industry:
Internet
Work:
Google
Software Engineer
Xsigo Systems - San Jose, CA 2006 - 2006
Manager, Engineering
Cisco Systems 1998 - 2006
Senior Manager
Samsung Telecommunications - Richardson, Texas 1997 - 1998
Senior Staff Engineer
Texas Instruments - VLSI Design Laboratory, Dallas 1987 - 1997
Member of Technical Staff
Education:
The University of Texas at Dallas 1996 - 2005
PhD, Electrical Engineering Southern Methodist University 1988 - 2005
Indian Institute of Science 1985 - 1987
ME, Computer Science and Automation Indian Institute of Technology, Kharagpur 1978 - 1983
B.Tech., Electronics & Communication
Honor & Awards:
1 Book 5+ Journal Publications 10+ Conference Publications 25+ Patents

Publications

Us Patents

Nested Measurement Period Switch Algorithm For Flow Control Of Available Bit Rate Atm Communications

View page
US Patent:
6377550, Apr 23, 2002
Filed:
Oct 27, 1998
Appl. No.:
09/179789
Inventors:
Sharat Prasad - San Jose CA
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G08C 1500
US Classification:
3702361, 370229, 370230, 370231, 370235, 370236, 370395, 370464, 370466, 370468, 370471, 370232, 370389, 3703951
Abstract:
An Asynchronous Transfer Mode (ATM) switch ( ) and method of operating the same to allocate Available Bit Rate (ABR) communications therethrough. The switch receives resource management (RM) cells over a sequence of measurement periods. A plurality of rate levels are defined, each associated with a measurement period of a corresponding duration; the measurement periods being nested. Saved and current values of the number of flows associated with each level, and saved and current values of the aggregate rates of these flows, are retained in memory. RM cells are received during the various measurement periods, and the various numbers and aggregate rates are maintained for each rate level, including the use of estimates for flows that have changed rate level. A bottleneck rate is determined as the larger of the ratio of ABR bandwidth to ABR flows, or the largest cell rate plus surplus bandwidth derived according to this sum. The bottleneck rate is then sent to the AT sources by backward-traveling RM cells, for adjustment of the ABR traffic.

Memory-Efficient Leaky Bucket Policer For Traffic Management Of Asynchronous Transfer Mode Data Communications

View page
US Patent:
6381214, Apr 30, 2002
Filed:
Oct 9, 1998
Appl. No.:
09/169604
Inventors:
Sharat Prasad - San Jose CA
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G01R 3108
US Classification:
3702301, 3702351, 37039521
Abstract:
A method and system for policing Asynchronous Transfer Mode (ATM) traffic, or for performing traffic shaping under ATM protocol, are disclosed. The disclosed system may be implemented into an ATM hub ( ), ATM switches ( ), or in network routers ( ), at which either a User-to-Network or Node-to-Network interface is present. Parameter memory ( ) in scheduling circuitry ( ) of these devices stores a difference field value (TAT-L)*, limit field value L*, and increment field value I for each virtual channel being handled. The difference field value (TAT-L)* is stored using fewer bits than used by a global timer ( ) to monitor global time and represent arrival time of cells, and both the difference field value (TAT-L)* and the limit field value L* are stored as twos complements of their actual value. Periodic resetting, to zero, of the difference field value (TAT-L)* is carried out by circuitry ( ), upon a determination that the least significant portion of the global time is later than the difference field value (TATL)* of the channel. Circuitry ( ) implements a leaky bucket algorithm to determine whether arrived cells are conforming, using the reduced bit width representations of the difference field value (TAT-L)* in parameter memory ( ).

Simplified Switch Algorithm For Flow Control Of Available Bit Rate Atm Communications

View page
US Patent:
6381216, Apr 30, 2002
Filed:
Oct 27, 1998
Appl. No.:
09/179183
Inventors:
Sharat Prasad - San Jose CA
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04L 1256
US Classification:
3702361, 370229, 370468
Abstract:
An Asynchronous Transfer Mode (ATM) switch ( ) and method of operating the same to allocate Available Bit Rate (ABR) communications therethrough is disclosed. The switch ( ) receives resource management (RM) cells over a sequence of measurement periods. Within each measurement period, the message flow associated with a received RM cell is identified, and a flag (SEEN ) in a memory array ( ) is interrogated to determine whether an RM cell for the message flow has yet been received in the measurement period. If not, a sum value (SUM) is updated with the current cell rate (CCR) of the flow and, if the CCR of the flow is equal to or greater than the highest cell rate (r ) yet measured in the measurement period, a highest cell rate field (r ) in memory and a count (m ) of flows having the highest cell rate are updated. Upon completion of the measurement period, a bottleneck rate is calculated by the switch ( ) as the larger of the ratio of ABR bandwidth to ABR flows, or the largest cell rate (r ) plus the surplus bandwidth; the surplus bandwidth is determined by subtracting the cell rate sum (SUM) from the ABR bandwidth, and dividing by the number (m ) of flows having the highest cell rate. The bottleneck rate is then sent to the ATM sources by backward-traveling RM cells, for adjustment of the ABR traffic.

Apparatus And Method For Reducing Queuing Memory Access Cycles Using A Distributed Queue Structure

View page
US Patent:
6735207, May 11, 2004
Filed:
Jun 13, 2000
Appl. No.:
09/593736
Inventors:
Sharat Chandra Prasad - San Jose CA
Tuchih Tsai - Santa Clara CA
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04L 1228
US Classification:
3703957, 370412, 370429
Abstract:
To reduce the number of memory access cycles required to process each data element in a data networking device having one or more queues and a corresponding set of data link structures, the queue and data link structures are implemented on separate memories. Each queue is maintained using separate receive and transmit queue structures. Similarly, the data memory linked list is separated into a data queue link and a data stack link. Each of these four memories comprises its own address and data bus, and all four memories may be accessed simultaneously by a controller. In a general case, processing a complete data transmission event (i. e. , a data element arrival and a data element departure) may be performed with a latency of at most three steps. In the first step, the transmit queue is read to obtain the old head pointer.

Network Switch And Method For Data Switching Using A Crossbar Switch Fabric With Output Port Groups Operating Concurrently And Independently

View page
US Patent:
6813274, Nov 2, 2004
Filed:
Mar 21, 2000
Appl. No.:
09/532341
Inventors:
Hiroshi Suzuki - Palo Alto CA
Paul Chang - San Jose CA
Sharat Prasad - San Jose CA
Chien Fang - Danville CA
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04L 1220
US Classification:
370412, 370386
Abstract:
A network switch and a method for data switching using a crossbar switch fabric with output port groups operating concurrently and independently that increases throughput and reduces scheduling complexity. The network switch includes a crossbar switch fabric, plurality of output port groups, and a plurality of input ports. The crossbar switch fabric includes a plurality of inputs and outputs. The plurality of output port groups operate concurrently and independently, and each output port group includes one or more output ports and is configured to receive a packet from one of the outputs of the crossbar switch and to send the packet to an output port. The plurality of input ports are coupled to an input of the crossbar switch fabric and configured to send packets to the crossbar switch fabric through the input of the crossbar switch fabric. Each input port includes a plurality of input buffer groups, and each input buffer group is assigned to send a packet for one of the output port groups such that there is a one-to-one correspondence between each of the input buffer groups and output port groups.

Method And System For Providing Operations, Administration, And Maintenance Capabilities In Packet Over Optics Networks

View page
US Patent:
7043541, May 9, 2006
Filed:
Sep 21, 2000
Appl. No.:
09/668253
Inventors:
Andreas Bechtolsheim - Stanford CA, US
Hiroshi Suzuki - Palo Alto CA, US
Marinica Rusu - Sunnyvale CA, US
Paul Frantz - Palo Alto CA, US
Sharat Prasad - San Jose CA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G06F 15/173
G06F 15/16
US Classification:
709223, 709236
Abstract:
A method for conveying management information across a network. The method includes receiving an Ethernet packet at a network element and modifying the packet by inserting a header in place of some or all of an unused portion of a preamble within the packet. The header is configured to provide support for network management. The method further includes transmitting the modified packet from the network element. The method may also include examining and updating the header at intermediate network elements and examining and replacing the header with the preamble at an egress network element.

Apparatus And Method For Distance Extension Of Fibre-Channel Over Transport

View page
US Patent:
7145877, Dec 5, 2006
Filed:
Mar 31, 2003
Appl. No.:
10/403396
Inventors:
Sriram Natarajan - Sunnyvale CA, US
Sharat Prasad - San Jose CA, US
Yu Deng - Milpitas CA, US
Yanfeng Wang - Fremont CA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04L 12/26
US Classification:
370235, 370252
Abstract:
The Fibre-Channel flow control mechanism is augmented to facilitate efficient data exchange between Fibre-Channel ports over extended distances. A supplemental buffer mechanism may be maintained as part of an interface to a transport network used to carry Fibre-Channel traffic. The transport network interface makes a remote Fibre-Channel port aware of the augmented local receiver buffer capacity by intercepting certain frames used in link establishment and substituting an enhanced buffer capacity for the local Fibre-Channel port's internal buffer capacity. This technique provides improved throughput and readily accommodates large distances and large frame sizes.

Method And System For Transporting Faults Across A Network

View page
US Patent:
7213178, May 1, 2007
Filed:
May 30, 2003
Appl. No.:
10/449260
Inventors:
Sharat Prasad - San Jose CA, US
Shankar Venkataraman - Campbell CA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G06F 11/00
US Classification:
714 43, 709223
Abstract:
A method for transmitting faults across networks operating with different protocols is disclosed. The method includes identifying a fault at a local node, mapping a fault indication bit into a carrier packet, and transmitting the fault indication over a network. The method further includes receiving an indication that the fault was received at a remote node.
Control profile
Sharat C Prasad from Saratoga, CA, age ~62 Get Report