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Shai Rotem

from Cupertino, CA
Age ~70
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Also known as:
Rotem Sivan
Connected to:
Jessica M Rotem, 42Martin S Rotemberg, 37Amie L Roten, 35Emily R Roten, 78Jacob A Roten, 32Jimmy D Roten, 58Jonathan L Roten, 39Kathleen A Roten, 75Lance Roten, 54Michael J Roten, 52

Shai Rotem Phones & Addresses

  • Cupertino, CA
  • 13015 Heather Ct, Beaverton, OR 97008
  • Sunnyvale, CA

Publications

Us Patents

Apparatus And Method For Parallel Processing And Self-Timed Serial Marking Of Variable Length Instructions

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US Patent:
59788992, Nov 2, 1999
Filed:
Dec 23, 1997
Appl. No.:
8/997457
Inventors:
Ran Ginosar - Nofit, IL
Rakefet Kol - Haifa, IL
Kenneth Scott Stevens - Hillsboro OR
Peter A. Beerel - Long Beach CA
Kenneth Yi Yun - San Diego CA
Christopher John Myers - Salt Lake City UT
Shai Rotem - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 930
US Classification:
712210
Abstract:
Optimal parallelization of necessarily serial operations is performed by speculative parallel processing and propagation of serial marking signals to indicate valid data. An exemplary instruction marking circuit for a computer system implementing such optimization includes a series of columns, each column corresponding to one byte of a fixed length instruction line, and a length decoder in each column. Each length decoder receives a byte of the respective column, and performs a length decode independently of the other length decoders. The length decoder asserts a length signal indicative of an instruction length when the byte is the first byte of an instruction. A marking unit arrangement is coupled to the length decoders, and operates to mark each column containing a first byte of an instruction as a function of the length signals asserted by the length decoders.

Efficient Self-Timed Marking Of Lengthy Variable Length Instructions

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US Patent:
59419822, Aug 24, 1999
Filed:
Dec 23, 1997
Appl. No.:
8/997461
Inventors:
Ran Ginosar - Nofit, IL
Rakefet Kol - Haifa, IL
Kenneth Scott Stevens - Hillsboro OR
Peter A. Beerel - Long Beach CA
Kenneth Yi Yun - San Diego CA
Christopher John Myers - Salt Lake City UT
Shai Rotem - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 930
US Classification:
712210
Abstract:
A self-timed instruction marking circuit includes a long instruction processing system to divide long instruction processing between two columns of the instruction marking circuit. Length decoders are interconnected across columns to signal the presence and length of long instructions. Self-timed marking can continue without alteration. The number of connections required by the instruction marking circuit are reduced. The marking process can be optimized to efficiently process all instructions by setting the definition of a long instruction such that commonly executed instructions are not included.

Apparatus And Method For Self-Timed Marking Of Variable Length Instructions Having Length-Affecting Prefix Bytes

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US Patent:
59480963, Sep 7, 1999
Filed:
Dec 23, 1997
Appl. No.:
8/997462
Inventors:
Ran Ginosar - Nofit, IL
Rakefet Kol - Haifa, IL
Kenneth Scott Stevens - Hillsboro OR
Peter A. Beerel - Long Beach CA
Kenneth Yi Yun - San Diego CA
Christopher John Myers - Salt Lake City UT
Shai Rotem - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 930
US Classification:
712210
Abstract:
A self-timed instruction marking circuit includes a prefix handling system for processing instruction bytes having prefix bytes. Length decoders receive instruction data bytes, and perform length decoding independently of the other length decoders in the instruction marking circuit. A length decoder determines whether a byte being processed is a prefix byte to an instruction. If a length-affecting prefix byte is found, the length decoder signals a subsequent length decoder to indicate that a prefix byte has been found. The subsequent length decoder uses the prefix signal to appropriately length decode the byte being processed by the subsequent length decoder. Signals are provided to continue the self-timed marking process. Prefix handling may also be used in a multiple marking unit configuration of an instruction marking circuit.

Branch Instruction Handling In A Self-Timed Marking System

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US Patent:
59319445, Aug 3, 1999
Filed:
Dec 23, 1997
Appl. No.:
8/996756
Inventors:
Ran Ginosar - Nofit, IL
Rakefet Kol - Haifa, IL
Kenneth Scott Stevens - Hillsboro OR
Peter A. Beerel - Long Beach CA
Kenneth Yi Yun - San Diego CA
Christopher John Myers - Salt Lake City UT
Shai Rotem - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 930
US Classification:
712239
Abstract:
An instruction execution pipeline in a computer system having variable-length instructions uses branch prediction to perform self-timed marking of instructions prior to decoding. Branch handling logic is provided in an instruction marking circuit to directly mark a target instruction of a predicted branch as the next instruction to be decoded. Additionally, a branch target FIFO may be used to store information about the location of the target instruction in the instruction stream.
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Shai Rotem from Cupertino, CA, age ~70 Get Report