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Shahin Mehdizad Taleie

from San Diego, CA
Age ~46

Shahin Taleie Phones & Addresses

  • 6326 Sagebrush Bend Way, San Diego, CA 92130
  • Laguna Niguel, CA
  • Tempe, AZ

Resumes

Resumes

Shahin Taleie Photo 1

Senior Staff Engineer And Manager

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Location:
San Diego, CA
Industry:
Semiconductors
Work:
Qualcomm Cdma Technologies
Principal Engineer, Manager

Qualcomm
Senior Staff Engineer and Manager

Intel Corporation May 2003 - Dec 2003
Intern

Andishehnegar 2000 - 2002
Network Engineer
Education:
Uc Irvine 2010 - 2013
Master of Business Administration, Masters
Arizona State University 2002 - 2008
Doctorates, Doctor of Philosophy, Electrical Engineering
University of Tehran 1996 - 2001
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Mixed Signal
Cmos
Analog Circuit Design
Ic
Circuit Design
Asic
Matlab
Cadence Virtuoso
Digital Signal Processors
Analog
Semiconductors
Rf
Simulations
Soc
Embedded Systems
Vlsi
Low Power Design
Signal Processing
Fpga
Integrated Circuit Design
Debugging
Electrical Engineering
Hardware Architecture
Analog Design
Dac
Computer Architecture
Rtl Design
Spice
Vhdl
Microprocessors
Eda
Algorithms
Digital Signal Processing
Pcb Design
Tcl
Team Leadership
Cross Functional Team Leadership
Technical Leadership
Lte
Wireless Broadband
Baseband
Envelope Tracking
Finfet
Shahin Taleie Photo 2

Staff Engineer

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Location:
San Diego, CA
Industry:
Telecommunications
Work:
Qualcomm
Staff Engineer

Publications

Us Patents

Wideband Digital To Analog Converter With Built-In Load Attenuator

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US Patent:
8169353, May 1, 2012
Filed:
Jan 13, 2010
Appl. No.:
12/686998
Inventors:
Dongwon Seo - San Diego CA, US
Ganesh R Saripalli - San Diego CA, US
Tongyu Song - San Diego CA, US
Shahin Mehdizad Taleie - San Diego CA, US
Derui Kong - San Diego CA, US
Assignee:
QUALCOMM, Incorporated - San Diego CA
International Classification:
H03M 1/66
US Classification:
341144, 341136
Abstract:
A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.

Buffer With Active Output Impedance Matching

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US Patent:
8410824, Apr 2, 2013
Filed:
Oct 22, 2009
Appl. No.:
12/604186
Inventors:
Shahin Mehdizad Taleie - San Diego CA, US
Jan Paul van der Wagt - Carlsbad CA, US
Assignee:
QUALCOMM, Incorporated - San Diego CA
International Classification:
H03K 3/00
US Classification:
327108
Abstract:
Techniques for designing a buffer capable of working with low supply voltages, and having active output impedance matching capability to optimize power delivery to a wide range of loads. In an exemplary embodiment, cascode transistors are provided in a buffer architecture employing common-source transistors having unequal width-to-length ratios (W/L) and a resistance having a corresponding fixed ratio to the load. At least one of the cascode transistors may be dynamically biased to minimize a difference between the drain voltages of the common-source transistors. In a further exemplary embodiment, the output impedance of the buffer may be actively tuned by selectively enabling a set of tuning transistors coupled in parallel with the load. Further techniques for providing a calibration mode and an operation mode are described.

Load Detecting Impedance Matching Buffer

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US Patent:
8610456, Dec 17, 2013
Filed:
Sep 23, 2011
Appl. No.:
13/241516
Inventors:
Liviu Chiaburu - Chandler AZ, US
Shahin Mehdizad Taleie - San Diego CA, US
Dongwon Seo - San Diego CA, US
Roy B. Silverstein - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H03K 17/16
US Classification:
326 30, 326 82, 326 21, 327108
Abstract:
A buffer amplifier has a power on state and a sleep state. During regular operation a coupling state of a load to an output node is detected using feedback voltage. In a sleep mode and in a power collapse mode a detection current is injected into the output node, to produce a voltage, and the coupling state of the load is detected from the voltage. Optionally, the detection current and detecting of the voltage on the output node is enables by a low duty cycle clock. Optionally, signals generated in detecting the coupling state are qualified through a debounce circuit.

Finite Impulse Response Digital To Analog Converter

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US Patent:
7528754, May 5, 2009
Filed:
Feb 8, 2007
Appl. No.:
11/672810
Inventors:
Bertan Bakkaloglu - Scottsdale AZ, US
Sayfe Kiaei - Fountain Hills AZ, US
Shahin Taleie - San Diego CA, US
Assignee:
Arizona Board of Regents - Tempe AZ
International Classification:
H03M 3/00
US Classification:
341143, 341136, 341144, 375295
Abstract:
A noise-shaped direct digital IF to RF DAC (DIF2RF) with embedded up-converter mixer is presented. The digital IF signal is noised shaped by a band-pass ΣΔ modulator with a single bit IF output followed by a semi-digital current-mode IF filter to attenuate out-of-band quantization noise. A current steering DAC combines scaled values of local oscillator (LO) signals as current sources for performing current steering and upconversion in a single cell.

Return-To-Zero (Rz) Digital-To-Analog Converter (Dac) For Image Cancellation

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US Patent:
20230097708, Mar 30, 2023
Filed:
Sep 22, 2021
Appl. No.:
17/448461
Inventors:
- San Diego CA, US
Nitz SAPUTRA - Burlingame CA, US
Dongwon SEO - San Diego CA, US
Shahin MEHDIZAD TALEIE - San Diego CA, US
International Classification:
H03M 1/06
Abstract:
Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first return-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.

Dynamic Transmission Front End And Digital-To-Analog Converter In Modem

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US Patent:
20210242958, Aug 5, 2021
Filed:
Jan 31, 2020
Appl. No.:
16/778608
Inventors:
- San Diego CA, US
Shahin Mehdizad Taleie - San Diego CA, US
Oren Matsrafi - Karkur, IL
Ronen Greenberger - Modiin, IL
Gal Keret - Raanana, IL
Yossi Waldman - Olesh, IL
Gideon Shlomo Kutz - Ramat Hasharon, IL
International Classification:
H04L 1/00
H03M 1/66
H04W 72/04
H04W 52/14
Abstract:
Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive a downlink control message from a base station indicating a modulation and coding scheme (MCS) associated with an uplink transmission, a number of layers associated with the uplink transmission, or both. The UE may determine to adjust (for example, reduce) a first number of bits based on the MCS, the number of layers, or both. The first number of bits may include an effective number of bits (ENOB) supported at a digital-to-analog converter (DAC) of the UE, a number of bits (NOB) supported at a transmission front end (TxFE) component of the UE, or both. The UE may transmit the uplink transmission to the base station according to the adjusted first number of bits.

Vehicle Sensor Data Acquisition And Distribution

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US Patent:
20200336541, Oct 22, 2020
Filed:
Apr 16, 2019
Appl. No.:
16/385400
Inventors:
- San Diego CA, US
Shahin Mehdizad Taleie - San Diego CA, US
International Classification:
H04L 29/08
G06F 11/30
G05D 1/00
H04L 29/06
Abstract:
Various aspects enable sensor data to be obtained from vehicles. Various aspects may enable data gathered by sensors of vehicles to be obtained by a data agency server and made available to third party client devices. In various aspects, a data agency server may direct a vehicle to drive from the vehicle's current location to a different specific location to gather a type of data. In some aspects, the type of data may be peripheral data that is not associated with driving operations of a vehicle. In some aspects, a data agency server may indicate one or more attributes of collection for the vehicle to utilize in gathering data. In some aspects, an attribute of collection may set a condition of the vehicle and/or the sensor utilized in gathering data. In some embodiments, vehicle owners/operators may be compensated for their vehicles being utilized to obtain data.

Apparatus And Method For Measuring Current Source Mismatches In Current-Steering Dac By Re-Using R2R Network

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US Patent:
20200099389, Mar 26, 2020
Filed:
Mar 28, 2019
Appl. No.:
16/367712
Inventors:
- San Diego CA, US
Nitz Saputra - Burlingame CA, US
Behnam Sedighi - La Jolla CA, US
Ashok Swaminathan - Cardiff CA, US
Honghao Ji - San Diego CA, US
Shahin Mehdizad Taleie - San Diego CA, US
Dongwon Seo - San Diego CA, US
International Classification:
H03M 1/74
H03M 1/68
H03M 1/78
Abstract:
A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.
Shahin Mehdizad Taleie from San Diego, CA, age ~46 Get Report