Shadi T Khasawneh

20200201671, Jun 25, 2020

Dec 20, 2018

16/228136

- Santa Clara CA, US
RAJSHREE CHABUKSWAR - Sunnyvale CA, US
Russell Fenger - Beaverton OR, US
Shadi Khasawneh - Austin TX, US
Vijay Dhanraj - Beaverton OR, US
Mukund Ramakrishna - Austin TX, US
Atsuo Kuwahara - Portland OR, US
Eugene Gorbatov - Hillsboro OR, US
MONICA GUPTA - Santa Clara CA, US
CHRISTINE M. LIN - Sunnyvale CA, US

Intel Corporation - Santa Clara CA

G06F 9/48
G06F 9/30
G06F 9/50

The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

20150095579, Apr 2, 2015

Sep 27, 2013

14/039424

Ahmad A. Samih - Austin TX, US
Shadi T. Khasawneh - Austin TX, US

G06F 12/08

711129

An apparatus and method for efficient handling of critical chunks. For example, one embodiment of an apparatus comprises a plurality of agents to perform a respective plurality of data processing functions, at least one of the data processing functions comprising transmitting and receiving chunks of data to and from a memory controller, respectively; a system agent to coordinate requests for transmitting and receiving the chunks of data to and from the memory controller, the system agent comprising: a memory for temporarily storing the chunks of data during transmission between the agents and the memory controller; and scheduling logic to prioritize critical chunks over non-critical chunks across multiple outstanding requests while ensuring that the non-critical chunks do not result in starvation.

20140281197, Sep 18, 2014

Mar 15, 2013

13/997437

Jose S. Niell - Franklin MA, US
Daniel F. Cutter - Maynard MA, US
James D. Allen - Austin TX, US
Deepak Limaye - Austin TX, US
Shadi T. Khasawneh - Austin TX, US

G06F 12/08

711105, 711118, 711146

In one embodiment, a conflict detection logic is configured to receive a plurality of memory requests from an arbiter of a coherent fabric of a system on a chip (SoC). The conflict detection logic includes snoop filter logic to downgrade a first snooped memory request for a first address to an unsnooped memory request when an indicator associated with the first address indicates that the coherent fabric has control of the first address. Other embodiments are described and claimed.