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Senaka K Kanakamedala

from San Jose, CA
Age ~39
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Related to:
Jayalakshmi Kanakamedala
Connected to:
Dana A Kanakaole, 53Justin K Kanakaole, 36Kavita G Kanakamedala, 42Anuradha Kanakasabapathi, 47Balamurugan Kanakasabai, 50Rama R Kanakapudi, 49Sabarigirish Kanakaraju, 41Nirav C Kanakia, 50Demetrios N Kanakis, 49Salah M Kanakri, 91

Senaka Kanakamedala Phones & Addresses

  • San Jose, CA
  • 1173 Calle Oriente, Milpitas, CA 95035
  • Boise, ID
  • Ruston, LA

Work

Company: Louisiana tech university Sep 2007 Position: Phd candidate

Education

School / High School: Louisiana Tech University- Ruston, LA Jan 2007 Specialities: Doctor of Philosophy in Engineering

Skills

Mems • Photolithography • Semiconductors • Nanotechnology • Matlab • Characterization • Simulations • Microfluidics • Etching • Microfabrication • Device Characterization • Comsol • Electronics • Sensors • Labview • Spc • C • Profilometer • Semiconductor Device • Pspice • Electrical Engineering • Icp • Coventorware • Tcad • Cell Culture • Nanofabrication • Dry Etching • Surface Profilometer • Solidworks • Autocad • Fabrication • Biosensors • Optical and Fluorescence Microscopy • Semiconductor Device Physics • Doe • Glucose Sensor • Glutamate Sensor • 3D Nand • Flash Memory • Nand Flash

Languages

English • Japanese

Industries

Semiconductors

Resumes

Resumes

Senaka Kanakamedala Photo 1

Senior Manager, Process Engineering

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Location:
950 south Main St, Milpitas, CA 95035
Industry:
Semiconductors
Work:
Louisiana Tech University since Sep 2007
PhD Candidate
Louisiana Tech University Aug 2006 - Sep 2007
Graduate Research Assistant
Jawaharlal Technology University Jun 2002 - May 2006
B-Tech in Electronics and Communications Engineering
Education:
Louisiana Tech University 2007 - 2011
Skills:
Mems
Photolithography
Semiconductors
Nanotechnology
Matlab
Characterization
Simulations
Microfluidics
Etching
Microfabrication
Device Characterization
Comsol
Electronics
Sensors
Labview
Spc
C
Profilometer
Semiconductor Device
Pspice
Electrical Engineering
Icp
Coventorware
Tcad
Cell Culture
Nanofabrication
Dry Etching
Surface Profilometer
Solidworks
Autocad
Fabrication
Biosensors
Optical and Fluorescence Microscopy
Semiconductor Device Physics
Doe
Glucose Sensor
Glutamate Sensor
3D Nand
Flash Memory
Nand Flash
Languages:
English
Japanese
Senaka Kanakamedala Photo 2

Senaka Kanakamedala San Jose, CA

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Education:
Louisiana Tech University
Ruston, LA
Jan 2007 to Jan 2011
Doctor of Philosophy in Engineering
Louisiana Tech University
Ruston, LA
Jan 2007 to Jan 2011
Master of Science in Electrical Engineering
Jawaharlal Nehru Technological University
Hyderabad, Andhra Pradesh
Jan 2002 to Jan 2006
Bachelor of Technology in Electronics & Communications Engineering
Senaka Kanakamedala Photo 3

Senaka Krishna Kanakamedala

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Publications

Us Patents

Three-Dimensional Memory Device Including Discrete Charge Storage Elements With Laterally-Protruding Profiles And Methods Of Making Thereof

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US Patent:
20220285386, Sep 8, 2022
Filed:
Mar 4, 2021
Appl. No.:
17/192463
Inventors:
- Addison TX, US
Raghuveer S. MAKALA - Campbell CA, US
Senaka KANAKAMEDALA - San Jose CA, US
Fei ZHOU - San Jose CA, US
International Classification:
H01L 27/11582
H01L 27/11556
H01L 27/11519
H01L 27/11524
H01L 27/1157
H01L 27/11565
Abstract:
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack and having lateral protrusions at levels of the electrically conductive layers, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner and located within volumes of the lateral protrusions. Each discrete memory element includes a vertical inner sidewall and a convex or stepped outer sidewall.

Three-Dimensional Memory Device Including Discrete Charge Storage Elements And Methods For Forming The Same

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US Patent:
20220278216, Sep 1, 2022
Filed:
Mar 1, 2021
Appl. No.:
17/189153
Inventors:
- ADDISON TX, US
Raghuveer S. MAKALA - Campbell CA, US
Fei ZHOU - San Jose CA, US
Senaka KANAKAMEDALA - San Jose CA, US
Ramy Nashed Bassely SAID - San Jose CA, US
International Classification:
H01L 29/423
H01L 27/11556
H01L 27/11582
H01L 27/11597
H01L 29/78
H01L 21/28
Abstract:
A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and memory opening fill structures located in the memory opening and including a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner. A subset of the insulating layers a lower insulating sublayer, an upper insulating sublayer overlying the lower insulating sublayer, and a center insulating sublayer located between and in contact with the lower insulating sublayer and the upper insulating sublayer.

Three-Dimensional Memory Device Including Multi-Bit Charge Storage Elements And Methods For Forming The Same

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US Patent:
20220254797, Aug 11, 2022
Filed:
Feb 8, 2021
Appl. No.:
17/169987
Inventors:
- ADDISON TX, US
Jiahui YUAN - Fremont CA, US
Senaka KANAKAMEDALA - San Jose CA, US
Raghuveer S. MAKALA - Campbell CA, US
Dana LEE - San Jose CA, US
International Classification:
H01L 27/11556
H01L 29/66
H01L 29/423
H01L 29/788
Abstract:
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from and is electrically isolated from the first memory material portion by at least one blocking dielectric material portion.

Three-Dimensional Memory Array Including Dual Work Function Floating Gates And Method Of Making The Same

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US Patent:
20220254798, Aug 11, 2022
Filed:
Jun 18, 2021
Appl. No.:
17/351720
Inventors:
- ADDISON TX, US
Yanli ZHANG - San Jose CA, US
Jiahui YUAN - Fremont CA, US
Raghuveer S. MAKALA - Campbell CA, US
Senaka KANAKAMEDALA - San Jose CA, US
International Classification:
H01L 27/11556
H01L 29/49
Abstract:
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures extending through the alternating stack, where each of the memory opening fill structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements is located at a level of a respective one of the electrically conductive layers between the respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from the first memory material portion. The second memory material portion has a different material composition from the first memory material portion.

Three Dimensional Semiconductor Device Containing Composite Contact Via Structures And Methods Of Making The Same

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US Patent:
20220246517, Aug 4, 2022
Filed:
Feb 3, 2021
Appl. No.:
17/166393
Inventors:
- Addison TX, US
Ramy Nashed Bassely SAID - San Jose CA, US
Rahul SHARANGPANI - Fremont CA, US
Senaka KANAKAMEDALA - San Jose CA, US
Raghuveer S. MAKALA - Campbell CA, US
International Classification:
H01L 23/522
H01L 23/528
H01L 23/532
H01L 27/11556
H01L 27/11582
H01L 21/768
Abstract:
A semiconductor structure includes at least one first semiconductor device located on a substrate, lower-level dielectric material layers embedding lower-level metal interconnect structures, at least one second semiconductor device and a dielectric material portion that overlie the lower-level dielectric material layers, at least one upper-level dielectric material layer, and an interconnection via structure vertically extending from the at least one upper-level dielectric material layer to a conductive structure that can be a node of the at least one first semiconductor device or one of lower-level metal interconnect structures. The interconnection via structure includes a transition metal layer and a fluorine-doped filler material portion in contact with the transition metal layer, composed primarily of a filler material selected from a silicide of the transition metal element or aluminum oxide, and including fluorine atoms.

Method Of Making A Three-Dimensional Memory Device Using Composite Hard Masks For Formation Of Deep Via Openings

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US Patent:
20220223470, Jul 14, 2022
Filed:
Mar 31, 2022
Appl. No.:
17/657521
Inventors:
- ADDISON TX, US
Monica TITUS - Santa Clara CA, US
Senaka KANAKAMEDALA - San Jose CA, US
Raghuveer S. MAKALA - Campbell CA, US
Rahul SHARANGPANI - Fremont CA, US
Adarsh RAJASHEKAR - Santa Clara CA, US
International Classification:
H01L 21/768
H01L 21/306
Abstract:
A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a mask layer over the alternating stack, forming a cavity in the mask layer, forming a first cladding liner on a sidewall of the cavity in the mask layer, and forming a via opening the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavity in the mask layer through the alternating stack using a combination of the first cladding liner and the mask layer as an etch mask.

Method Of Making A Three-Dimensional Memory Device Using Composite Hard Masks For Formation Of Deep Via Openings

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US Patent:
20220208556, Jun 30, 2022
Filed:
Jun 23, 2021
Appl. No.:
17/355955
Inventors:
- Addison TX, US
Senaka KANAKAMEDALA - San Jose CA, US
Rahul SHARANGPANI - Fremont CA, US
Raghuveer S. MAKALA - Campbell CA, US
Monica TITUS - Santa Clara CA, US
International Classification:
H01L 21/311
H01L 23/535
H01L 27/11556
H01L 27/11529
H01L 27/11582
H01L 27/11573
H01L 27/11597
H01L 27/11592
H01L 21/768
Abstract:
An alternating stack of first material layers and second material layers can be formed over a semiconductor material layer. A patterning film is formed over the alternating stack, and openings are formed through the patterning film. Via openings are formed through the alternating stack at least to a top surface of the semiconductor material layer by performing a first anisotropic etch process that transfers a pattern of the openings in the patterning film. A cladding liner can be formed on a top surface of the patterning film and sidewalls of the openings in the pattering film. The via openings can be vertically extended through the semiconductor material layer at least to a bottom surface of the semiconductor material layer by performing a second anisotropic etch process employing the cladding liner as an etch mask.

Method Of Making A Three-Dimensional Memory Device Using Composite Hard Masks For Formation Of Deep Via Openings

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US Patent:
20220208600, Jun 30, 2022
Filed:
Oct 22, 2021
Appl. No.:
17/508036
Inventors:
- Addison TX, US
Senaka KANAKAMEDALA - San Jose CA, US
Raghuveer S. MAKALA - Campbell CA, US
Rahul SHARANGPANI - Fremont CA, US
Monica TITUS - Santa Clara CA, US
Adarsh RAJASHEKHAR - Santa Clara CA, US
International Classification:
H01L 21/768
H01L 21/306
H01L 21/308
Abstract:
A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer. The via openings are vertically extended at least through the source-level semiconductor layer by performing a second anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.
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Senaka K Kanakamedala from San Jose, CA, age ~39 Get Report