Saurabh Morarka

20220238714, Jul 28, 2022

Apr 19, 2022

17/723582

- Santa Clara CA, US
Anand Murthy - Portland OR, US
Glenn Glass - Beaverton OR, US
Saurabh Morarka - Hillsboro OR, US
Chandra Mohapatra - Beaverton OR, US

H01L 29/78
H01L 29/66
H01L 29/10
H01L 29/06
H01L 29/32

Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

20230006063, Jan 5, 2023

Sep 9, 2022

17/941814

- Bronxville NY, US
Anand Murthy - Portland OR, US
Glenn Glass - Beaverton OR, US
Saurabh Morarka - Hillsboro OR, US
Chandra Mohapatra - Beaverton OR, US

H01L 29/78
H01L 29/66
H01L 29/10
H01L 29/06
H01L 29/32

Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

20210305436, Sep 30, 2021

Mar 25, 2020

16/830112

- Santa Clara CA, US
Saurabh MORARKA - Hillsboro OR, US
Carlos NIEVA-LOZANO - Beaverton OR, US
Kalyan KOLLURU - Portland OR, US
Biswajeet GUHA - Hillsboro OR, US
Chung-Hsun LIN - Portland OR, US
Brian GREENE - Portland OR, US
Tahir GHANI - Portland OR, US

H01L 29/93
H01L 29/06
H01L 21/02
H01L 29/66

Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

20200259018, Aug 13, 2020

Feb 8, 2019

16/270826

- Santa Clara CA, US
Hyung-Jin Lee - Portland OR, US
Saurabh Morarka - Hillsboro OR, US
Guannan Liu - Portland OR, US
Qiang Yu - San Jose CA, US
Bernhard Sell - Portland OR, US
Mark Armstrong - Portland OR, US

Intel Corporation - Santa Clara CA

H01L 29/78
H01L 29/51
H01L 29/49
H01L 29/423
H01L 29/06
H01L 29/08
H01L 29/66
H01L 29/40

Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

20200105747, Apr 2, 2020

Sep 28, 2018

16/147205

- Santa Clara CA, US
Mark ARMSTRONG - Portland OR, US
Saurabh MORARKA - Hillsboro OR, US
Carlos NIEVA-LOZANO - Beaverton OR, US
Ayan KAR - Portland OR, US

H01L 27/08
H01L 29/93
H01L 29/66
H01L 27/105

An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.

20190334034, Oct 31, 2019

Jul 11, 2019

16/509421

- Santa Clara CA, US
Anand MURTHY - Portland OR, US
Glenn GLASS - Beaverton OR, US
Saurabh MORARKA - Hillsboro OR, US
Chandra MOHAPATRA - Beaverton OR, US

H01L 29/78
H01L 29/66
H01L 29/10
H01L 29/06
H01L 29/32

Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

20180240874, Aug 23, 2018

Sep 25, 2015

15/754150

- Santa Clara CA, US
SAURABH MORARKA - Hillsboro OR, US
RITESH JHAVERI - Hillsboro OR, US
GLENN A. GLASS - Portland OR, US
SZUYA S. LIAO - Portland OR, US
ANAND S. MURTHY - Portland OR, US

INTEL CORPORATION - Santa Clara CA

H01L 29/08
H01L 21/225
H01L 21/306
H01L 29/66
H01L 29/78
H01L 29/06
H01L 29/417

Techniques are disclosed for resistance reduction under transistor spacers. In some instances, the techniques include reducing the exposure of source/drain (S/D) dopants to thermal cycles, thereby reducing the diffusion and loss of S/D dopants to surrounding materials. In some such instances, the techniques include delaying the epitaxial deposition of the doped S/D material until near the end of the transistor formation process flow, thereby avoiding the thermal cycles earlier in the process flow. For example, the techniques may include replacing the S/D regions (e.g., native fin material in the regions to be used for the transistor S/D) with sacrificial S/D material that can then be selectively etched and replaced by highly doped epitaxial S/D material later in the process flow. In some cases, the selective etch may be performed through S/D contact trenches formed in overlying insulator material over the sacrificial S/D.

20160204256, Jul 14, 2016

Sep 26, 2013

14/912594

Michael JACKSON - Portland OR, US
Anand MURTHY - Portland OR, US
Glenn GLASS - Beaverton OR, US
Saurabh MORARKA - Hillsboro OR, US
Chandra MOHAPATRA - Beaverton OR, US

H01L 29/78
H01L 29/66
H01L 29/10

Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.