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Sameer P Chhajed

from Boise, ID
Age ~43
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Connected to:
Abhishek Chhajed, 38Adarsh Chhajed, 43Divya Chhajed, 40Mukesh K Chhajer, 61Vikas K Chhajer, 39Arti Chhajta, 38Jennifer Chham, 32Dan Chhan, 41Sherland R Chhangur, 74Khum D Chhantyal, 57

Sameer Chhajed Phones & Addresses

  • Boise, ID
  • Poughkeepsie, NY
  • Columbia, SC
  • 2151 12Th St, Troy, NY 12180 (518) 272-1093
  • Raleigh, NC
  • Revere, MA
  • El Paso, TX
  • 2151 12Th St, Troy, NY 12180 (518) 441-5392

Work

Company: Micron technology, inc. May 2013 Position: Cmos engineer emerging memory

Education

School / High School: Rensselaer Polytechnic Institute- Troy, NY Dec 2010 Specialities: Doctor of Philosophy in Electrical Engineering

Emails

s***[email protected]

Resumes

Resumes

Sameer Chhajed Photo 1

Process Integration Engineer - Emerging Memory

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Location:
8000 south Federal Way, Boise, ID 83716
Industry:
Semiconductors
Work:
Micron Technology
Process Integration Engineer - Emerging Memory
Micron Technology Dec 2012 - Apr 2013
Led R and D Process Integration Lead
Micron Technology Dec 2011 - Nov 2012
Led R and D Process Integration Engineer
Pohang University of Science and Technology Nov 2010 - Oct 2011
Post-Doctoral Research Associate
Rensselaer Polytechnic Institute Aug 2007 - Dec 2010
Doctoral Student
Education:
Rensselaer Polytechnic Institute 2007 - 2010
Rensselaer Polytechnic Institute 2002 - 2004
Master of Science, Masters, Electrical Engineering College of Engineering Pune 1998 - 2002
Bachelor of Engineering, Bachelors, Electrical Engineering
Skills:
Characterization
Semiconductors
Simulations
R&D
Jmp
Cmos
Thin Films
Pvd
Sensors
Photolithography
Metrology
Optoelectronics
Solid State Lighting
Semiconductor Fabrication
Device Characterization
Semiconductor Device
Optics
Device Physics
Photonics
Problem Solving
Ellipsometry
Scanning Electron Microscopy
Vacuum Technology
Solid State Physics
Business Acumen
Gan
Process Integration
Data Analysis
Failure Analysis
Decision Making
Logical Approach
Compound Semiconductors
Semiconductor Process
Semiconductor Failure Analysis
Failure Mode and Effects Analysis
Statistical Data Analysis
Semiconductor Device Physics
Yield Enhancement
Statistical Process Control
8D Problem Solving
Semiconductor Industry
Semiconductor Process Technology
Mosfet
Sputtering
Plasma Etch
Dry Etch
Languages:
English
Sameer Chhajed Photo 2

Engineer

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Location:
Boise, ID
Industry:
Broadcast Media
Work:
Cognizant Productions Llc
Engineer
Sameer Chhajed Photo 3

Sameer Chhajed Boise, ID

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Work:
Micron Technology, Inc.

May 2013 to 2000
CMOS Engineer Emerging Memory
Micron Technology, Inc.
Boise, ID
Dec 2012 to Apr 2013
LED R&D Process Integration Lead
Micron Technology, Inc.
Boise, ID
Dec 2011 to Nov 2012
LED Process Integration Engineer (Advanced Lab)
POSTECH, KOREA

Nov 2010 to Oct 2011
Post-Doctoral Research Associate
RPI
Troy, NY
Aug 2007 to Dec 2010
Doctoral Student
Troy Research Corporation
Troy, NY
Jan 2007 to Dec 2009
Sr. Research Engineer
University of South Carolina
Columbia, SC
Jan 2005 to Oct 2006
Research Assistant
Future Chips Constellation, RPI
Troy, NY
Aug 2002 to Dec 2004
Research Assistant
Education:
Rensselaer Polytechnic Institute
Troy, NY
Dec 2010
Doctor of Philosophy in Electrical Engineering
Rensselaer Polytechnic Institute
Troy, NY
Dec 2004
Master of Science in Electrical Engineering
Government College of Engineering
Pune, Maharashtra
Aug 2002
Bachelor of Engineering in Electrical Engineering

Publications

Us Patents

Encapsulant Shapes For Light Emitting Devices Lacking Rotational Symmetry Designed To Enhance Extraction Of Light With A Particular Linear Polarization

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US Patent:
7819557, Oct 26, 2010
Filed:
Jun 24, 2008
Appl. No.:
12/213790
Inventors:
Martin F. Schubert - Troy NY, US
Sameer Chhajed - Troy NY, US
Jong Kyu Kim - Watervliet NY, US
E. Fred Schubert - Troy NY, US
Cheolsoo Sone - Suwon-si, KR
Assignee:
Rensselaer Polytechnic Institute - Troy NY
Samsung Electro-Mechanics Co., Ltd. - Suwon
International Classification:
F21V 3/00
F21V 5/00
US Classification:
36231102, 362 19, 362255, 362293, 36231106, 257100
Abstract:
The light-emitting device includes a light source and a transparent encapsulating material that is shaped to modify the polarization anisotropy of light emitted by the light source in at least one direction.

Reflector Shapes For Light Emitting Diode-Polarized Light Sources

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US Patent:
20080316751, Dec 25, 2008
Filed:
Jun 24, 2008
Appl. No.:
12/213791
Inventors:
Martin F. Schubert - Troy NY, US
Sameer Chhajed - Troy NY, US
Jong Kyu Kim - Watervliet NY, US
E. Fred Schubert - Troy NY, US
Jaehee Cho - Suwon-si, KR
Assignee:
Rensselaer Polytechnic Institute - Troy NY
Samsung Electro-Mechanics Co., Ltd. - Suwon
International Classification:
F21V 7/00
US Classification:
362296
Abstract:
A light-emitting device including a light source that exhibits polarization anisotropy and a reflector that is shaped so that for light emitted in at least two directions from the light source, the angle between the dominant polarization directions after reflecting from the reflector is smaller than the angle between the dominant polarization directions before reflecting from the reflector. In the light-emitting device the light source may be a light-emitting diode chip or one of a plurality of light sources.

Ultra-Low Reflectance Broadband Omni-Directional Anti-Reflection Coating

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US Patent:
20110120554, May 26, 2011
Filed:
Mar 27, 2009
Appl. No.:
12/736278
Inventors:
Sameer Chhajed - Troy NY, US
Jong Kyu Kim - Watervliet NY, US
Mei-Ling Kuo - Troy NY, US
Frank W. Mont - Poughkeepsie NY, US
David J. Poxson - Troy NY, US
E. Fred Schubert - Troy NY, US
Martin F. Schubert - Troy NY, US
International Classification:
H01L 31/0232
B32B 7/02
B32B 18/00
G02B 1/11
H01L 31/18
B82Y 30/00
US Classification:
136259, 4282921, 42831111, 428113, 428216, 20419226, 359586, 438 72, 977902, 257E31119
Abstract:
An anti-reflection coating has an average total reflectance of less than 10%, for example less than 5.9% such as from 4.9% to 5.9%, over a spectrum of wavelengths of 400-1100 nm and a range of angles of incidence of 0-90 degrees with respect to a surface normal of the anti-reflection coating. An anti-reflection coating has a total reflectance of less than 10%, for example less than 6% such as less than 4%, over an entire spectrum of wavelengths of 400-1600 nm and an entire range of angles of incidence of 0-70 degrees with respect to a surface normal of the anti-reflection coating.

On-Die Formation Of Single-Crystal Semiconductor Structures

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US Patent:
20230042701, Feb 9, 2023
Filed:
Aug 9, 2021
Appl. No.:
17/397725
Inventors:
- Boise ID, US
Anish A. Khandekar - Boise ID, US
Hung-Wei Liu - Meridian ID, US
Sameer Chhajed - Boise ID, US
International Classification:
H01L 27/11514
H01L 21/02
Abstract:
Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

Methods Of Incorporating Leaker Devices Into Capacitor Configurations To Reduce Cell Disturb, And Capacitor Configurations Incorporating Leaker Devices

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US Patent:
20210391343, Dec 16, 2021
Filed:
Jun 10, 2020
Appl. No.:
16/897556
Inventors:
- Boise ID, US
Sanket S. Kelkar - Boise ID, US
Ashonita A. Chavan - Boise ID, US
Sameer Chhajed - Boise ID, US
Adriel Jebin Jacob Jebaraj - Meridian ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27/11507
H01L 27/1159
H01L 27/11504
H01L 27/11587
H01L 49/02
Abstract:
Some embodiments include a capacitor having a container-shaped bottom portion. The bottom portion has a first region over a second region. The first region is thinner than the second region. The first region is a leaker region and the second region is a bottom electrode region. The bottom portion has an interior surface that extends along the first and second regions. An insulative material extends into the container shape. The insulative material lines the interior surface of the container shape. A conductive plug extends into the container shape and is adjacent the insulative material. A conductive structure extends across the conductive plug, the insulative material and the first region of the bottom portion. The conductive structure directly contacts the insulative material and the first region of the bottom portion, and is electrically coupled with the conductive plug. Some embodiments include methods of forming assemblies.

Integrated Assemblies Comprising Hydrogen Diffused Within Two Or More Different Semiconductor Materials, And Methods Of Forming Integrated Assemblies

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US Patent:
20210375868, Dec 2, 2021
Filed:
Aug 6, 2021
Appl. No.:
17/396049
Inventors:
- Boise ID, US
Yi Fang Lee - Boise ID, US
Haitao Liu - Boise ID, US
Durai Vishak Nirmal Ramaswamy - Boise ID, US
Ramanathan Gandhi - Boise ID, US
Karthik Sarpatwari - Boise ID, US
Scott E. Sills - Boise ID, US
Sameer Chhajed - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27/105
H01L 27/092
H01L 27/12
H01L 29/66
H01L 29/267
H01L 29/423
H01L 29/786
H01L 29/24
Abstract:
Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

Transistor And Methods Of Forming Integrated Circuitry

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US Patent:
20210265502, Aug 26, 2021
Filed:
May 11, 2021
Appl. No.:
17/317674
Inventors:
- Boise ID, US
Sameer Chhajed - Boise ID, US
Jeffery B. Hull - Boise ID, US
Anish A. Khandekar - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 29/78
H01L 27/108
H01L 29/66
H01L 21/02
H01L 29/04
Abstract:
A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μmof one another. Other embodiments, including methods, are disclosed.

Transistor And Methods Of Forming Integrated Circuitry

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US Patent:
20210043769, Feb 11, 2021
Filed:
Aug 9, 2019
Appl. No.:
16/536590
Inventors:
- Boise ID, US
Sameer Chhajed - Boise ID, US
Jeffery B. Hull - Boise ID, US
Anish A. Khandekar - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 29/78
H01L 27/108
H01L 29/04
H01L 21/02
H01L 29/66
Abstract:
A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μmof one another. Other embodiments, including methods, are disclosed.
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Sameer P Chhajed from Boise, ID, age ~43 Get Report