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Samantha Edirisooriya Phones & Addresses

  • 640 Vinedo Ln, Tempe, AZ 85284
  • Phoenix, AZ
  • Maricopa, AZ
  • Iowa City, IA

Publications

Us Patents

Methods And Apparatus For Cache Intervention

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US Patent:
6983348, Jan 3, 2006
Filed:
Nov 25, 2002
Appl. No.:
10/303931
Inventors:
Sujat Jamil - Chandler AZ,
Hang Nguyen - Tempe AZ,
Samantha J. Edirisooriya - Tempe AZ,
David E. Miner - Chandler AZ,
R. Frank O'Bleness - Tempe AZ,
Steven J. Tu - Phoenix AZ,
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711146, 711142, 711143, 711145
Abstract:
Methods and Apparatus for cache-to-cache transfers upon snooping a cache interconnect to detect a memory read request associated with a cache memory block cached in a first cache and a second cache. Upon a cache hit to a first and a second cache, supplying the cached memory block from the first cache or the second cache to a third cache based on a predetermined arbitration hierarchy.

Method, System, And Apparatus For An Efficient Cache To Support Multiple Configurations

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US Patent:
2004001, Jan 22, 2004
Filed:
Jul 19, 2002
Appl. No.:
10/199580
Inventors:
Samantha Edirisooriya - Tempe AZ,
Sujat Jamil - Chandler AZ,
David Miner - Chandler AZ,
R. O'Bleness - Tempe AZ,
Steven Tu - Phoenix AZ,
International Classification:
G06F012/00
G06F012/12
US Classification:
711/163000, 711/136000, 711/144000
Abstract:
The invention supports a replacement scheme for a cache that supports multiple configurations.

Apparatus And Method For Power Optimized Replay Via Selective Recirculation Of Instructions

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US Patent:
7725683, May 25, 2010
Filed:
Sep 25, 2003
Appl. No.:
10/671844
Inventors:
Sujat Jamil - Chandler AZ,
Hang Nguyen - Tempe AZ,
Samantha J. Edirisooriya - Tempe AZ,
David E. Miner - Chandler AZ,
R. Frank O'Bleness - Tempe AZ,
Steven J. Tu - Phoenix AZ,
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 9/00
US Classification:
712214
Abstract:
A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a detected blocking condition. Once enqueued, instructions contained within the recirculation queue may be reissued once a blocking condition of an instruction within the recirculation queue is satisfied. Accordingly, a power optimized replay scheme as described herein optimizes power while retaining the advantages provided by selectively replaying of blocked instructions to improve power efficiency.

Method And Apparatus For Optimizing Line Writes In Cache Coherent Systems

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US Patent:
7757046, Jul 13, 2010
Filed:
Sep 30, 2002
Appl. No.:
10/262363
Inventors:
Sujat Jamil - Chandler AZ,
Hang T. Nguyen - Tempe AZ,
Samantha J. Edirisooriya - Tempe AZ,
David E. Miner - Chandler AZ,
R. Frank O'Bleness - Tempe AZ,
Steven J. Tu - Phoenix AZ,
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/12
US Classification:
711133, 711159, 711156
Abstract:
A method and apparatus for optimizing line writes in cache coherent systems. A new cache line may be allocated without loading data to fill the new cache line when a store buffer coalesces enough stores to fill the cache line. Data may be loaded to fill the line if an insufficient number of stores are coalesced to fill the entire cache line. The cache line may be allocated by initiating a read and invalidate request and asserting a back-off signal to cancel the read if there is an indication that the coalesced stores will fill the cache line.

Apparatus And Method For Arbitrating Heterogeneous Agents In On-Chip Busses

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US Patent:
7765349, Jul 27, 2010
Filed:
Sep 22, 2008
Appl. No.:
12/284396
Inventors:
Samantha J. Edirisooriya - Tempe AZ,
Sujat Jamil - Chandler AZ,
David E. Miner - Chandler AZ,
R. Frank O'Bleness - Tempe AZ,
Steven J. Tu - Phoenix AZ,
Hang T. Nguyen - Tempe AZ,
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 13/36
G06N 7/06
US Classification:
710113, 710107, 710111, 370462
Abstract:
A bus control system includes N bus agents each having a corresponding bus request delay and M bus agents each having a corresponding bus request delay. A controller determines the bus request delays of the N bus agents and the M bus agents and grants concurrent ownership of a bus to each of the N bus agents and non-concurrent ownership of the bus to each of the M bus agents based on the determination. M and N are integers greater than 1.

Power Optimized Replay Of Blocked Operations In A Pipilined Architecture

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US Patent:
7966477, Jun 21, 2011
Filed:
May 18, 2010
Appl. No.:
12/782184
Inventors:
Sujat Jamil - Chandler AZ,
Hang Nguyen - Tempe AZ,
Samantha J. Edirisooriya - Tempe AZ,
David E. Miner - Chandler AZ,
R. Frank O'Bleness - Tempe AZ,
Steven J. Tu - Phoenix AZ,
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 9/00
US Classification:
712214
Abstract:
A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a detected blocking condition. Once enqueued, instructions contained within the recirculation queue may be reissued once a blocking condition of an instruction within the recirculation queue is satisfied. Accordingly, a power optimized replay scheme as described herein optimizes power while retaining the advantages provided by selectively replaying of blocked instructions to improve power efficiency.

Method And System For Syndrome Generation And Data Recovery

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US Patent:
8156406, Apr 10, 2012
Filed:
Jan 29, 2008
Appl. No.:
12/022009
Inventors:
Samantha J. Edirisooriya - Tempe AZ,
Gregory W. Tse - Tempe AZ,
Mark A. Schmisseur - Phoenix AZ,
Robert L. Sheffield - Chandler AZ,
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 29/00
US Classification:
714770
Abstract:
A method and system for syndrome generation and data recovery is described. The system includes a parity generator coupled to one or more storage devices to generate parity for data recovery. The parity generator includes a first comparator to generate a first parity factor based on data in one or more of the storage devices, a multiplier to multiply data from one or more of the storage devices with a multiplication factor to generate a product, a second comparator coupled to the multiplier to generate a second parity factor based at least in part on the product, and a selector to choose between the first parity factor and the second parity factor.

Implementing Direct Access Caches In Coherent Multiprocessors

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US Patent:
8533401, Sep 10, 2013
Filed:
Dec 30, 2002
Appl. No.:
10/331688
Inventors:
Samantha J. Edirisooriya - Tempe AZ,
Sujat Jamil - Chandler AZ,
David E. Miner - Chandler AZ,
R. Frank O'Bleness - Tempe AZ,
Steven J. Tu - Phoenix AZ,
Hang T. Nguyen - Tempe AZ,
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711141, 711113
Abstract:
Non-processor agents, such as bus agents, may directly access processor caches. A coherency protocol ensures that cache coherency is maintained.
Samantha J Edirisooriya from Tempe, AZ, age ~58 Get Report