Sujat Jamil - Chandler AZ,
Hang T. Nguyen - Tempe AZ,
Samantha J. Edirisooriya - Tempe AZ,
David E. Miner - Chandler AZ,
R. Frank O'Bleness - Tempe AZ,
Steven J. Tu - Phoenix AZ,
Intel Corporation - Santa Clara CA
A method and apparatus for optimizing line writes in cache coherent systems. A new cache line may be allocated without loading data to fill the new cache line when a store buffer coalesces enough stores to fill the cache line. Data may be loaded to fill the line if an insufficient number of stores are coalesced to fill the entire cache line. The cache line may be allocated by initiating a read and invalidate request and asserting a back-off signal to cancel the read if there is an indication that the coalesced stores will fill the cache line.