Ryuji Orita

7694055, Apr 6, 2010

Oct 15, 2005

11/251334

Ryuji Orita - Redmond WA, US
Susumu Arai - Portland OR, US
Brian D. Allison - Rochester MN, US
Patrick M. Bland - Raleigh NC, US

International Business Machines Corporation - Armonk NY

G06F 13/24

710260, 710261, 710262, 710263, 710264, 710265, 710266, 710267, 710268, 710269, 710240

Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.

7793291, Sep 7, 2010

Dec 22, 2004

11/020409

Susumi Arai - Kenmore WA, US
Ryuji Orita - Redmond WA, US

International Business Machines Corporation - Armonk NY

G06F 9/46
G06F 9/00
G06F 11/00
G06F 1/00

718100, 718105, 718108, 712228, 712229, 713100, 713300, 713320, 713322, 714 47

A method and apparatus are provided for thermal management of a multiprocessor computer system. The temperatures of the various processors within a multiprocessor system are monitored. When a processor is identified as overheated, a dummy process will be assigned to it, causing all other processes to be put on hold, thereby reducing the heat output of that processor. When the temperature of the processor lowers below another predetermined value, then the dummy process is terminated.

8041936, Oct 18, 2011

Oct 28, 2007

11/926083

Ryuji Orita - Redmond WA, US
Mark A. Brandyberry - Austin TX, US
Mehul M. Shah - Austin TX, US
Sean P. Brogan - Kenmore WA, US

International Business Machines Corporation - Armonk NY

G11C 29/00
G06F 11/22

713 2, 713 1, 713100, 714723, 714776

The last value of an element of a computing system is continually stored within a first register. The element is cleared during any restart or reset of the computing system. The last value is relevant to debugging of the computing system when the computing system fails to perform as expected and/or as desired. Upon receiving an instruction to reset the computing system via a first reset signal corresponding to pressing of a reset button or a second reset signal corresponding to a baseboard management controller issuing a reset command, the last value of the element as stored within the first register is copied to a second register. The computing system is then reset. The last value of the element as stored within the second register persists within the second register during this type of reset, but is cleared during any other reset or restart of the computing system.

8103884, Jan 24, 2012

Jun 25, 2008

12/146085

Thomas M. Brey - Cary NC, US
Wesley M. Felter - Austin TX, US
Sumeet Kochar - Apex NC, US
Charles R. Lefurgy - Austin TX, US
Ryuji Orita - Redmond WA, US
Malcolm S. Ware - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 1/26

713300, 713320

Methods and products for managing power consumption of a computer and computers for which power consumption is managed. The computer includes the computer including a computer processor and embodiments of the present invention include providing, by an in-band power manger to an out-of-band power manager, a proposed performance state (‘p-state’) for the computer processor; determining, by the out-of-band power manager, in dependence upon a power setpoint and currently-measured operating metrics of the computer processor, whether to approve the proposed p-state; and if the out-of-band power manager approves the proposed p-state, setting operating parameters of the computer processor according to the approved p-state.

8307220, Nov 6, 2012

Jun 25, 2008

12/146056

Thomas M. Brey - Cary NC, US
Wesley M. Felter - Austin TX, US
Sumeet Kochar - Apex NC, US
Charles R. Lefurgy - Austin TX, US
Ryuji Orita - Redmond WA, US
Malcolm S. Ware - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 1/32

713300, 713310, 713320, 713321, 713322, 713323, 713324, 713330, 713340

Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.

8504875, Aug 6, 2013

Dec 28, 2009

12/647828

Ryuji Orita - Redmond WA, US
Barry A. Kritt - Raleigh NC, US
Charles D. Bauman - Sammamish WA, US
Sumeet Kochar - Apex NC, US
Jeremy K. Holland - Gig Harbor WA, US
Karen A. Taylor - Carnation WA, US

International Business Machines Corporation - Armonk NY

G06F 11/00

714 30, 714 31, 714 34, 714 3814, 714 26

A computing device includes a processor, firmware, a hardware component, and a debugging module. The firmware stores error decoding logic particular to the computing device. The hardware component detects an error in the computing device, and responsively issues an interrupt and halts the processor such that the processor cannot execute any more computer-readable code. The debugging module loads the logic from the firmware at reset and executes the logic responsive to the interrupt. The debugging module does not use the processor to execute the logic, the firmware is not part of the debugging module, and the debugging module is not part of the hardware component. The firmware may also store a mapping between registers of the hardware component and field-replaceable hardware units of the computing device, which the debugging module loads at reset and uses when executing the error decoding logic to determine which unit has caused the error.

20040123009, Jun 24, 2004

Dec 18, 2002

10/323475

Edward Holley - Kirkland WA, US
Koichi Kii - Bellevue WA, US
Ryuji Orita - Kirkland WA, US
Christopher Ruggles - Seattle WA, US

International Business Machines Corporation - Armonk NY

H05K007/10
G06F013/00

710/302000

A facility is provided for hotplugging multiple adapters into a system having a bus with a plurality of adapter receiving hotplug slots. The facility includes connecting multiple hotplug adapters to multiple hotplug slots of the bus, and automatically determining a bus speed for the bus that the multiple hotplug slots and the multiple hotplug adapters connected thereto support. The automatically determining is transparent to a user of the system making the hotplug adapter connections and is independent of an order of connection of the multiple hotplug adapters to the multiple hotplug slots.

20070239917, Oct 11, 2007

Dec 9, 2005

11/299152

Ryuji Orita - Redmond WA, US
Mehul Shah - Austin TX, US
Sumeet Kochar - Apex NC, US

G06F 13/24

710268000

Interrupts are routed within a multiple-processor system, such as a single computing device having multiple processors. Such a computerized system includes a number of processors and a mechanism. Each processor is capable of processing an interrupt. The mechanism, such as a Southbridge controller, receives the interrupt and routes it to a selected processor. The selected processor processes the interrupt via entry into a mode related to the interrupt. The interrupt may be a system management interrupt (SMI), and the mode a system management mode (SMM). The other processors operate normally and are not affected by processing of the interrupt, and do not have to enter the mode. These other processors can continue executing code as before, and may receive and process other types of interrupts. The system may include another mechanism, such as a complex programmable logic device (CPLD), specifying the selected processor.