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Russell Enderby Phones & Addresses

  • Atlanta, GA
  • 635 Morning Creek Ct, Suwanee, GA 30024
  • Cumming, GA
  • Woodstock, GA
  • Coral Springs, FL
  • Lynchburg, VA
  • Austin, TX
  • Blacklick, OH

Work

Company: Broadcom Position: Senior staff software engineer

Skills

Ieee 802.11 • Cable Modems • Device Drivers

Industries

Computer Networking

Resumes

Resumes

Russell Enderby Photo 1

Russell Enderby

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Location:
204 Weatherstone Xing, Woodstock, GA 30188
Industry:
Computer Networking
Work:
Broadcom
Senior Staff Software Engineer

Gainesville Direct Net
President

Gainesville Direct Net
Owner

The Enderby Family
Principle
Skills:
Ieee 802.11
Cable Modems
Device Drivers

Business Records

Name / Title
Company / Classification
Phones & Addresses
Russell Enderby
President, Treasurer, Secretary, Principal
Gdn Networks, Inc
Nonclassifiable Establishments
3706 NW 43 St, Gainesville, FL 32606
3255 Lawrenceville Suwanee Rd, Suwanee, GA 30024
3255 Lawrencevle Suwanee, Suwanee, GA 30024

Publications

Us Patents

Method And System For Reducing Storage Requirements For Program Code In A Communication Device

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US Patent:
7278002, Oct 2, 2007
Filed:
Nov 30, 2005
Appl. No.:
11/290855
Inventors:
Derek Winters - Duluth GA, US
Allen Walston - Atlanta GA, US
Jeff Andrews - Norcross GA, US
Robert Easterling - Woodstock GA, US
Russell Enderby - Woodstock GA, US
Assignee:
Arris International, Inc. - Suwanee GA
International Classification:
G06F 12/02
US Classification:
711165, 711103, 711105
Abstract:
A software routine that writes downloaded updated operating system software over existing application code to flash memory of a cable modem in an inverted arrangement. If the download process is interrupted before the update can be verified, a pointer still points to the existing code to facilitate update-interruption recovery. After verifying a successful update, a new pointer is generated that points to the updated operating system. Then, updated application code can be downloaded and stored in the flash memory over the old operating system code. Thus, each time an update is performed, the location of the operating system within the flash memory with respect to the location of the application code is inverted. This allows the size of flash memory to be reduced, as only one copy of the operating system and application code must be stored, while retaining capability to recovery from an incomplete download.

Packet Handler For High-Speed Data Networks

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US Patent:
7796583, Sep 14, 2010
Filed:
Jul 17, 2002
Appl. No.:
10/196884
Inventors:
Russell T. Enderby - Suwanee GA, US
Assignee:
Nortel Networks Limited - St. Laurent, Quebec
International Classification:
H04L 12/66
US Classification:
370353, 370356, 370412, 370413, 725106
Abstract:
An improved packet handler for VoIP cable modems and other high-speed digital devices includes a direct communication link via hardware among internal processing components. Incoming and outgoing digital information packets are filtered into MAC packets, voice PDU packets, and non-voice PDU packets, such that priority can be given to relaying voice packets and minimizing potential voice delay within the cable network. Hardware components, including specialized logic circuitry, modify voice packets to an appropriate signal form for subsequent signal processing or signal transmission. Proprietary bus communication protocols can also be provided to facilitate relay of packets between a central processing unit (CPU) and a digital signal processor (DSP) within a VoIP cable modem. Line cards including subscriber line interface circuit (SLIC) and subscriber line audio processing circuit (SLAC) components provide analog-to-digital (A/D) and digital-to-analog (D/A) conversion functionality.

Multi-Stage Deep Packet Inspection For Lightweight Devices

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US Patent:
7853689, Dec 14, 2010
Filed:
Oct 12, 2007
Appl. No.:
11/871866
Inventors:
Russell Enderby - Suwanee GA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 15/173
US Classification:
709224, 709203, 709217, 709219, 709225, 726 22, 726 24
Abstract:
A system and method for the multi-stage analysis of incoming packets. Three stages are used, each of which addresses a particular category of threat by examining the headers and/or payload of each packet (“deep packet inspection”). The first stage detects incoming viruses or worms. The second stage detects malicious applications. The third stage detects attempts at intrusion. These three stages operate in sequence, but in alternative embodiments of the invention, they may be applied in a different order. These three stages are followed by a fourth stage that acts as a verification stage. If any of the first three stages detects a possible attack, then the packet or packets that have been flagged are routed to a central verification facility. In an embodiment of the invention, the verification facility is a server, coupled with a database. Here, suspect packets are compared to entries in the database to more comprehensively determine whether or not the packets represent an attempt to subvert the information processing system.

Packet Handler For High Speed Data Networks

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US Patent:
8259710, Sep 4, 2012
Filed:
Aug 2, 2010
Appl. No.:
12/848715
Inventors:
Russell T. Enderby - Suwanee GA, US
Assignee:
Rockstar Bidco, L.P. - New York NY
International Classification:
H04L 12/66
US Classification:
370353, 370356, 370412, 370413, 725106
Abstract:
An improved packet handler for VoIP cable modems and other high-speed digital devices includes a direct communication link via hardware among internal processing components. Incoming and outgoing digital information packets are filtered into MAC packets, voice PDU packets, and non-voice PDU packets, such that priority can be given to relaying voice packets and minimizing potential voice delay within the cable network. Hardware components, including specialized logic circuitry, modify voice packets to an appropriate signal form for subsequent signal processing or signal transmission. Proprietary bus communication protocols can also be provided to facilitate relay of packets between a central processing unit (CPU) and a digital signal processor (DSP) within a VoIP cable modem. Line cards including subscriber line interface circuit (SLIC) and subscriber line audio processing circuit (SLAC) components provide analog-to-digital (A/D) and digital-to-analog (D/A) conversion functionality.

Method And System For Reducing Storage Requirements For Program Code In A Communication Device

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US Patent:
20030167373, Sep 4, 2003
Filed:
Feb 28, 2003
Appl. No.:
10/376381
Inventors:
Derek Winters - Duluth GA, US
Allen Walston - Atlanta GA, US
Jeff Andrews - Norcross GA, US
Robert Easterling - Woodstock GA, US
Russell Enderby - Woodstock GA, US
International Classification:
G06F012/00
US Classification:
711/103000, 711/104000
Abstract:
A software routine that writes downloaded updated operating system software over existing application code to flash memory of a cable modem in an inverted arrangement. If the download process is interrupted before the update can be verified, a pointer still points to the existing code to facilitate update-interruption recovery. After verifying a successful update, a new pointer is generated that points to the updated operating system. Then, updated application code can be downloaded and stored in the flash memory over the old operating system code. Thus, each time an update is performed, the location of the operating system within the flash memory with respect to the location of the application code is inverted. This allows the size of flash memory to be reduced, as only one copy of the operating system and application code must be stored, while retaining capability to recovery from an incomplete download.

Packet Handler For High Speed Data Networks

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US Patent:
20120294306, Nov 22, 2012
Filed:
Aug 6, 2012
Appl. No.:
13/567180
Inventors:
Russell T. ENDERBY - Suwanee GA, US
Assignee:
ROCKSTAR BIDCO, LP - New York NY
International Classification:
H04L 12/66
US Classification:
370355
Abstract:
An improved packet handler for VoIP cable modems and other high-speed digital devices includes a direct communication link via hardware among internal processing components. Incoming and outgoing digital information packets are filtered into MAC packets, voice PDU packets, and non-voice PDU packets, such that priority can be given to relaying voice packets and minimizing potential voice delay within the cable network. Hardware components, including specialized logic circuitry, modify voice packets to an appropriate signal form for subsequent signal processing or signal transmission. Proprietary bus communication protocols can also be provided to facilitate relay of packets between a central processing unit (CPU) and a digital signal processor (DSP) within a VoIP cable modem. Line cards including subscriber line interface circuit (SLIC) and subscriber line audio processing circuit (SLAC) components provide analog-to-digital (A/D) and digital-to-analog (D/A) conversion functionality.

System For Reducing Bandwidth Usage On A Multicast Computer Network

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US Patent:
20210152384, May 20, 2021
Filed:
Nov 20, 2019
Appl. No.:
16/689398
Inventors:
Russell Enderby - Atlanta GA, US
International Classification:
H04L 12/18
H04N 21/6405
H04L 12/58
Abstract:
According to some embodiments, a system for reducing bandwidth usage is disclosed. The system comprises a computer server that receives a request to initiate a multicast communication over a computer network and a computer readable medium comprising instructions that perform a method when executed by the centralized computer server. The method comprises initiating a multicast communication and assigning a unique identifier to the multicast communication. A set of messages associated with the unique identifier is received. If it is determined that a number of messages is greater than a pre-determined number of messages, determining a location of each of the users and grouping the users into a first group and into a second group where the first group are all located within a pre-defined radius based on a first determined location and the second group are all located within a pre-defined radius based on a second determined location.

Packet Handler For High Speed Data Networks

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US Patent:
20140321457, Oct 30, 2014
Filed:
Jul 11, 2014
Appl. No.:
14/329456
Inventors:
- Plano TX, US
Russell T. ENDERBY - Suwanee GA, US
International Classification:
H04L 12/741
H04M 7/00
US Classification:
370352
Abstract:
An improved packet handler for VoIP cable modems and other high-speed digital devices includes a direct communication link via hardware among internal processing components. Incoming and outgoing digital information packets are filtered into MAC packets, voice PDU packets, and non-voice PDU packets, such that priority can be given to relaying voice packets and minimizing potential voice delay within the cable network. Hardware components, including specialized logic circuitry, modify voice packets to an appropriate signal form for subsequent signal processing or signal transmission. Proprietary bus communication protocols can also be provided to facilitate relay of packets between a central processing unit (CPU) and a digital signal processor (DSP) within a VoIP cable modem. Line cards including subscriber line interface circuit (SLIC) and subscriber line audio processing circuit (SLAC) components provide analog-to-digital (A/D) and digital-to-analog (D/A) conversion functionality.
Russell T Enderby from Atlanta, GA, age ~52 Get Report