Search

Rupert J Brauch

from Truckee, CA
Age ~55
Get Report
Also known as:
Rupert A Brauch, Rupert J Branch, Rupert Bauch, M Brauch Rupert
Phone and address:
10771 Whitehorse Rd, Truckee, CA 96161
(408) 506-5741
Related to:
Peter Brauch
Connected to:
Christopher Brauch, 30Roberta Brauch, 37Tonya T Brauch, 51Jessica Braucher, 31Joe F Braucher, 47Tammy A Braucher, 65Anna A Brauchler, 75Christopher Brauchli, 35Emily BrauchleGeorge H Brauchler, 82

Rupert Brauch Phones & Addresses

  • 10771 Whitehorse Rd, Truckee, CA 96161 (408) 506-5741
  • Marina, CA
  • 927 Eton Way, Sunnyvale, CA 94087 (408) 735-8305
  • Cupertino, CA
  • 1372 Cherrywood Sq, San Jose, CA 95117 (408) 378-4022
  • Palo Alto, CA
  • Hanover, NH
  • Santa Clara, CA
  • Lebanon, NH
  • 927 Eton Way, Sunnyvale, CA 94087 (408) 378-4022

Work

Company: Intel Nov 2010 Position: Software engineer

Education

Degree: MS School / High School: Stanford University 1994 to 1996 Specialities: Computer Science

Skills

Computer Architecture • High Performance Computing • Processors • Operating Systems • Debugging • Unix • Compilers • X86

Industries

Semiconductors

Resumes

Resumes

Rupert Brauch Photo 1

Rupert Brauch

View page
Location:
Truckee, CA
Industry:
Semiconductors
Work:
Intel since Nov 2010
Software Engineer
NVIDIA Dec 2008 - Oct 2010
Senior Software Engineer
Sun Microsystems Nov 1998 - Dec 2008
Senior Staff Engineer - Software
Hewlett Packard Jun 1996 - Nov 1998
Member Technical Staff
MCC May 1992 - Aug 1994
Member Technical Staff
Education:
Stanford University 1994 - 1996
MS, Computer Science Oberlin College 1989 - 1991
BA, Philosophy
Skills:
Computer Architecture
High Performance Computing
Processors
Operating Systems
Debugging
Unix
Compilers
X86

Publications

Us Patents

Mechanism For Software Register Renaming And Load Speculation In An Optimizer

View page
US Patent:
6526572, Feb 25, 2003
Filed:
Feb 9, 2000
Appl. No.:
09/500518
Inventors:
Rupert Brauch - San Jose CA
David A. Dunn - San Jose CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06I 945
US Classification:
717154, 717131, 717152, 717153, 712226, 712227
Abstract:
The inventive mechanism operates to optimize program efficiency in a two phase process. In the first phase, the mechanism conducts a dependency analysis on the instructions to determine dependency relationships between the various instructions in an instruction window. The mechanism thereby identifies candidates for register renaming and instruction speculation, and provisionally performs the renaming and speculation operations, while preserving information which is preferably used to reverse these operations in the second phase if it is determined that the operations may be effectively rescheduled. In the second phase, the mechanism determines whether the optimizing operations, renaming and speculation, were beneficial in each case. Each instruction for which the mechanism finds the optimizing operation to be beneficial will generally remain in optimized form. Optimizing operations found not be beneficial are generally reversed by the mechanism.

Instruction-Optimizing Processor With Branch-Count Table In Hardware

View page
US Patent:
20130311752, Nov 21, 2013
Filed:
May 18, 2012
Appl. No.:
13/475755
Inventors:
Rupert Brauch - Sunnyvale CA, US
Madhu Swarna - Portland OR, US
Ross Segelken - Portland OR, US
David Dunn - Sammamish WA, US
Ben Hertzberg - Santa Clara CA, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G06F 9/30
US Classification:
712208, 712E09028
Abstract:
A processing system comprising a microprocessor core and a translator. Within the microprocessor core is arranged a hardware decoder configured to selectively decode instructions for execution in the microprocessor core, and, a logic structure configured to track usage of the hardware decoder. The translator is operatively coupled to the logic structure and configured to selectively translate the instructions for execution in the microprocessor core, based on the usage of the hardware decoder as determined by the logic structure.

Method And Apparatus For Handling Asynchronous Signals While Emulating System Calls

View page
US Patent:
6421635, Jul 16, 2002
Filed:
Nov 2, 1998
Appl. No.:
09/184845
Inventors:
Bharath Chandramohan - San Clara CA
Rupert Brauch - Palo Alto CA
David A. Dunn - San Jose CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 945
US Classification:
703 26, 703 23
Abstract:
The invention determines whether any asynchronous signals are pending and then delivers any such pending signals to the emulated application before the control is transferred to the operating system. A first mechanism sets a global flag, and checks to determine if any signals are pending. If there are pending signals, the emulator halts the emulation of the system call, and delivers the signal to the emulated application. A second mechanism handles signals that arrive after the first mechanism has performed its check. This mechanism checks to see if the global flag is set when a signal arrives. If the flag is set, then the signal is delivered immediately. If the flag is not set, then the signal is deferred. A third mechanism establishes a watch state at the beginning of the emulation, which would be changed by any action of the operating system. When a signal comes in, the emulator checks the watch state.

Method And Apparatus For Implementing And Maintaining A Stack Of Predicate Values With Stack Synchronization Instructions In An Out Of Order Hardware Software Co-Designed Processor

View page
US Patent:
20160179538, Jun 23, 2016
Filed:
Dec 19, 2014
Appl. No.:
14/576915
Inventors:
- Santa Clara CA, US
Jayesh Iyer - Santa Clara CA, US
Sebastian Winkel - Los Altos CA, US
Polychronis Xekalakis - Barcelona, GR
Howard H. Chen - Sunnyvale CA, US
Rupert Brauch - Sunnyvale CA, US
International Classification:
G06F 9/30
Abstract:
Embodiments of a method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions. In one embodiment the apparatus is an out of order hardware/software co-designed processor including instructions to explicitly manage the predicate register stack to maintain stack consistency across branches of executing that push a variable number of predicate values onto the predicate stack. In one embodiment the stack-based predicate register implementation enables early branch calculation and early branch misprediction recovery via early renaming of predicate registers.

Instruction And Logic For A Logical Move In An Out-Of-Order Processor

View page
US Patent:
20150277911, Oct 1, 2015
Filed:
Mar 28, 2014
Appl. No.:
14/229179
Inventors:
Rupert Brauch - Sunnyvale CA, US
Raul Martinez - Barcelona, ES
Naveen Neelakantam - Mountain View CA, US
Thang Vu - Barsbuettel, DE
International Classification:
G06F 9/30
Abstract:
A processor includes allocation unit with logic to receive a logical move instruction. The logical move instruction includes a source logical register as a source parameter and a destination logical register as a destination parameter. The source logical register is assigned to a source physical register and the destination logical register is assigned to a destination physical register. The allocation unit includes logic to assign a first value of the source logical register to the destination logical register and to maintain a second value of the destination physical register before and after the assignment of the first value to the destination logical register.

Profiling Code Portions To Generate Translations

View page
US Patent:
20140281392, Sep 18, 2014
Filed:
Mar 14, 2013
Appl. No.:
13/828865
Inventors:
- Santa Clara CA, US
Alexander Klaiber - Mountain View CA, US
Ross Segelken - Portland OR, US
David Dunn - Sammamish WA, US
Ben Hertzberg - Santa Clara CA, US
Rupert Brauch - Sunnyvale CA, US
Thomas Kistler - Palo Alto CA, US
Guillermo J. Rozas - Los Gatos CA, US
Madhu Swarna - Portland OR, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G06F 9/30
US Classification:
712208
Abstract:
The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.
Control profile
Rupert J Brauch from Truckee, CA, age ~55 Get Report