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Roger Christopher Griesmer

from Murphy, TX
Age ~53
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Also known as:
Roger C Griesmer, Roger G Griesmer, Roger C Griesner, Roger G Griesner, Roger C Griesme, Rodger Griesmer, Griesmer Rc, Roger N
Phone and address:
179 Moonlight Dr, Plano, TX 75094
(972) 422-8617
Related to:
Josef GriesmerNathan T Barr, 34Lindsay M Barr, 36Sharon Frank, 90Amanda M KujawaAshley Frank, 39
Connected to:
Henry J Griesmer, 86Lynn D Griesmeyer, 73Robert Griesmeyer, 39Trevor C Griesmeyer, 50Gary R Griesmyer, 82David A Grieson, 39Bret C Griess, 55Dean Griess, 97Eric Griess, 33Jacqueline Griess, 46

Roger Griesmer Phones & Addresses

  • 179 Moonlight Dr, Murphy, TX 75094 (972) 422-8617
  • Gleason, WI
  • Bowie, TX
  • Edgar, WI
  • Bryan, TX
  • Jacksboro, TX
  • Dallas, TX
  • Colton, TX
  • Mosinee, WI
  • 179 Moonlight Dr, Murphy, TX 75094

Work

Company: Texas instruments Position: Senior member technical staff

Education

Degree: BSEE School / High School: Michigan Technological University 1990 to 1992 Specialities: Electrical Engineering

Skills

Static Timing Analysis • Timing Closure • Physical Design • Soc • Asic • Primetime • Ic • Eda • Vlsi • Verilog • Semiconductors • Integrated Circuit Design • Tcl • Drc • Physical Verification • Lvs • Clock Tree Synthesis • Floorplanning • Cmos • Low Power Design • Mixed Signal • Rtl Design • Logic Synthesis • Functional Verification • Signal Integrity • Dft • Power Management • Rtl Coding

Industries

Semiconductors

Resumes

Resumes

Roger Griesmer Photo 1

Senior Member Technical Staff At Texas Instruments

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Location:
Dallas, TX
Industry:
Semiconductors
Work:
Texas Instruments
Senior Member Technical Staff
Education:
Michigan Technological University 1990 - 1992
BSEE, Electrical Engineering
Skills:
Static Timing Analysis
Timing Closure
Physical Design
Soc
Asic
Primetime
Ic
Eda
Vlsi
Verilog
Semiconductors
Integrated Circuit Design
Tcl
Drc
Physical Verification
Lvs
Clock Tree Synthesis
Floorplanning
Cmos
Low Power Design
Mixed Signal
Rtl Design
Logic Synthesis
Functional Verification
Signal Integrity
Dft
Power Management
Rtl Coding

Publications

Us Patents

Integrated Circuit With Programmable Fuse Array

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US Patent:
6876594, Apr 5, 2005
Filed:
Dec 19, 2003
Appl. No.:
10/739520
Inventors:
Roger C. Griesmer - Murphy TX, US
Robert L. Pitts - Dallas TX, US
Bryan D. Sheffield - Rowlett TX, US
Mark J. Jensen - Allen TX, US
Vinod J. Menezes - Bangalore, IN
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C007/00
US Classification:
3652257, 365200, 365 96
Abstract:
An integrated circuit (IC). The integrated circuit comprises an array () of data cells arranged in a plurality of rows and a plurality of columns. Each of the data cells comprises an electrically programmable fuse (), and each electrically programmable fuse comprises a current path for providing a first digital state when the current path is left intact and for providing a second digital state when the current path is destroyed. Each row of the plurality of rows comprises at least one cell reserved for providing a protection indicator for the row, wherein the protection indicator is selected from a set consisting of read protection and write protection. The integrated circuit also comprises control circuitry () for selectively destroying the programmable fuse in selected ones of the data cells in a programmation mode. The integrated circuit also comprises control circuitry () for reading selected ones of the data cells in a read mode.

Contact Fuse Which Does Not Touch A Metal Layer

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US Patent:
8093716, Jan 10, 2012
Filed:
Jul 29, 2005
Appl. No.:
11/192825
Inventors:
Robert L. Pitts - Dallas TX, US
Bryan Sheffield - McKinney TX, US
Roger Griesmer - Murphy TX, US
Joe McPherson - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 23/34
US Classification:
257723, 361760, 361761, 174260
Abstract:
The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse further comprises a second semiconductor layer that forms a blow junction interface with the fuse layer. The blow junction interface is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer to the fuse layer.
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Roger Christopher Griesmer from Murphy, TX, age ~53 Get Report