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Robert W Bollish

from Austin, TX
Age ~68
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Also known as:
Robert William Bollish, Robert W Ballish
Phone and address:
11606 Sundown Trl, Austin, TX 78739
(512) 282-8863
Related to:
Marvin F Edwards, 82Gayle G Edwards, 75Estate O PogorzelskiAlan Pogorzelski, 69Brenda L Taylor, 66Joan Pogorzelski, 90Melanie Pogorzelski, 29
Connected to:
Lynn A Bollish, 61Alex M Bollman, 51Amanda Bollman, 39Anna L Bollman, 73Bernard M Bollman, 58Christy L Bollman, 54Dylan Bollman, 33Elizabeth B Bollmann, 85Ellen R Bollman, 58Isaac D Bollman, 32

Robert Bollish Phones & Addresses

  • 11606 Sundown Trl, Austin, TX 78739 (512) 282-8863
  • Missouri City, TX
  • 11606 Sundown Trl, Austin, TX 78739 (512) 470-9946

Work

Position: Professional/Technical

Education

Degree: High school graduate or higher

Emails

r***[email protected]

Resumes

Resumes

Robert Bollish Photo 1

Robert Bollish

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Location:
Austin, TX
Industry:
Semiconductors
Work:
National Semiconductor Aug 2010 - Jun 2011
Director Test Development, Power Management Ic's
Freescale Semiconductor Aug 2010 - Jun 2011
Retired From
Boy Scouts of America Jan 2008 - Aug 2010
Capital Area Council Advancement Chair
Freescale Semiconductor Apr 2009 - Dec 2009
Test Engineering Manager, Networking and Multimedia Group
Freescale Semiconductor Sep 2004 - Apr 2009
Test Engineering Manager, Cellular Products Group
Education:
Mid - Plains College 1979 - 1980
Skills:
Semiconductors
Ic
Testing
Microcontrollers
Soc
Test Engineering
Electronics
Product Engineering
Semiconductor Industry
Network Processors
Integrated Circuit Design
Power Management
Digital Signal Processors
Rf
Manufacturing
Asic
Debugging
Wireless
Engineering Management
Analog
Microprocessors
Processors
Yield
Mixed Signal
Embedded Systems
Process Improvement
Dft
Management
Engineering
Silicon
Test Equipment
Failure Analysis
Analog Circuit Design
Cmos
Vlsi
Fpga
Pcb Design
Hardware Architecture
Tcl
Eda
Robert Bollish Photo 2

Robert Bollish

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Publications

Us Patents

Apparatus For Performing Wafer Level Testing Of Integrated Circuit Dice

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US Patent:
55043690, Apr 2, 1996
Filed:
Nov 21, 1994
Appl. No.:
8/342960
Inventors:
Edward C. Dasse - Austin TX
Robert W. Bollish - Austin TX
Alfredo Figueroa - Austin TX
James H. Carlquist - Austin TX
Thomas R. Yarbrough - Buda TX
Charles F. Toewe - Austin TX
Kelvin L. Holub - Austin TX
Marcus R. Burton - Dripping Springs TX
Kenneth J. Long - Austin TX
Walid S. Ballouli - Austin TX
Assignee:
Motorola Inc. - Schaumburg IL
International Classification:
H01L 2166
G01R 3100
G01R 3128
US Classification:
257620
Abstract:
A semiconductor wafer (20) having integrated circuit dice (22), wafer conductors (42-47, 50-53), and wafer contact pads (38) formed thereon. The wafer conductors (42-47, 50-53) are used to transfer electrical signals to and from the integrated circuit dice (22) on semiconductor wafer (20) so that wafer level testing and burn-in can be performed on the integrated circuit dice (22). In accordance with one embodiment of the present, each wafer conductor (45, 52) is electrically coupled to the same bonding pad (78) on each integrated circuit dice (22). Each wafer conductor (42-47, 50-53) includes at least a portion of conductor (42-47) which overlies the upper surface of at least one integrated circuit dice (22).

Method And Apparatus For Performing Wafer Level Testing Of Integrated Circuit Dice

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US Patent:
53995058, Mar 21, 1995
Filed:
Jul 23, 1993
Appl. No.:
8/096094
Inventors:
Edward C. Dasse - Austin TX
Robert W. Bollish - Austin TX
Alfredo Figueroa - Austin TX
James H. Carlquist - Austin TX
Thomas R. Yarbrough - Buda TX
Charles F. Toewe - Austin TX
Kelvin L. Holub - Austin TX
Marcus R. Burton - Dripping Springs TX
Kenneth J. Long - Austin TX
Walid S. Ballouli - Austin TX
Shih K. Cheng - Scottsdale AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2166
US Classification:
437 8
Abstract:
A semiconductor wafer (20) having integrated circuit dice (22), wafer conductors (42-47, 50-53), and wafer contact pads (38) formed thereon. The wafer conductors (42-47, 50-53) are used to transfer electrical signals to and from the integrated circuit dice (22) on semiconductor wafer (20) so that wafer level testing and burn-in can be performed on the integrated circuit dice (22). In accordance with one embodiment of the present, each wafer conductor (45, 52) is electrically coupled to the same bonding pad (78) on each integrated circuit dice (22). Each wafer conductor (42-47, 50-53) includes at least a portion of conductor (42-47) which overlies the upper surface of at least one integrated circuit dice (22).

Apparatus For Performing Wafer-Level Testing Of Integrated Circuits Where The Wafer Uses A Segmented Conductive Top-Layer Bus Structure

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US Patent:
56545886, Aug 5, 1997
Filed:
Jun 7, 1995
Appl. No.:
8/487671
Inventors:
Edward C. Dasse - Austin TX
Robert W. Bollish - Austin TX
Alfredo Figueroa - Austin TX
James H. Carlquist - Austin TX
Thomas R. Yarbrough - Buda TX
Charles F. Toewe - Austin TX
Kelvin L. Holub - Austin TX
Marcus R. Burton - Dripping Springs TX
Kenneth J. Long - Austin TX
Walid S. Ballouli - Austin TX
Shih King Cheng - Scottsdale AZ
Assignee:
Motorola Inc. - Schaumburg IL
International Classification:
G01R 3100
G01R 3128
H01L 2166
US Classification:
257754
Abstract:
Wafer level testing of a wafer (500) is accomplished by dividing the integrated circuits of the wafer into a plurality of segmented bus regions (514, 516, and 518 for example). Each bus region is formed having its own set of test conductors (520-530) wherein each set of test conductors are isolated from all other sets of test conductors on the wafer. Each test conductor has at least one contact pad (531-546) where each contact pad lies within a periphery of the integrated circuits' active areas. By forming pads over ICs and by sub-dividing the bus structure of test conductive lines, more high powered ICs can be tested in a wafer-level manner with fewer problems associated with speed, power, throughput, and routing problems.
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Robert W Bollish from Austin, TX, age ~68 Get Report