Resumes
Resumes
Robert Bignell Phones & Addresses
-
1041 Lanark Ct, Sunnyvale, CA 94087
-
Brighton, MI
-
41832 Old Bridge Rd, Canton, MI 48188
-
1625 Meadowlark Ln, Sunnyvale, CA 94087
Education
Degree:
Associate degree or higher
Public records
Vehicle Records
Robert Bignell
View pageAddress:
1625 Meadowlark Ln, Sunnyvale, CA 94087
VIN:
WBAVB73537VF50614
Make:
BMW
Model:
3 SERIES
Year:
2007
Publications
Us Patents
Cross Bar Multipath Resource Controller System And Method
View pageUS Patent:
7996592, Aug 9, 2011
Filed:
May 2, 2001
Appl. No.:
09/847991
Inventors:
Jason Seung-Min Kim - San Jose CA, US
Robert Alan Bignell - San Jose CA, US
Robert Alan Bignell - San Jose CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 12/00
G06F 13/00
G06F 13/00
US Classification:
710244, 710317
Abstract:
A cross bar multipath resource controller system and method permit multiple processors in a computer system to access various resource of the computer system, such as memory or peripherals, with zero blocking access. In particular, each processor has its own bus so that the processors can each independently access different resources in the computer system simultaneously.
Autonomous Power-Gating During Idle In A Multi-Core System
View pageUS Patent:
20130198549, Aug 1, 2013
Filed:
Jan 27, 2012
Appl. No.:
13/360559
Inventors:
Matthew Raymond LONGNECKER - San Jose CA, US
Scott Alan Williams - San Jose CA, US
Sagheer Ahmad - Cupertino CA, US
Robert Alan Bignell - San Jose CA, US
Venkata Krishna Reddy Dumpa - Santa Clara CA, US
Scott Alan Williams - San Jose CA, US
Sagheer Ahmad - Cupertino CA, US
Robert Alan Bignell - San Jose CA, US
Venkata Krishna Reddy Dumpa - Santa Clara CA, US
International Classification:
G06F 1/32
US Classification:
713324
Abstract:
To preserve power and increase the overall efficiency of the CPU, the platform idle driver causes the power gate controller to cut power to the idle core. Such power gating is autonomous, i.e., the operating system and the other cores are not involved. In operation, the platform idle driver first prepares the core and the power gate controller for power gating the core. The platform idle driver then triggers the power gating. The power gate controller monitors interrupts released by the interrupt controller, and if any on the released interrupts are associated with the power gated core, the power gate controller resumes dispersing power to the core.
Pipelined Microprocessor That Prevents The Cache From Being Read When The Contents Of The Cache Are Invalid
View pageUS Patent:
56597126, Aug 19, 1997
Filed:
May 26, 1995
Appl. No.:
8/452659
Inventors:
Robert J. Divivier - San Jose CA
Robert Bignell - San Jose CA
Robert Bignell - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G06F 1200
US Classification:
395481
Abstract:
The power consumed by a cache memory when the cache is read is reduced by utilizing a cache access circuit to prevent the cache from being read when the information stored in the cache is invalid, such as when the processor is powered up, reset by a user, or an invalidation bit is set.