Richard Steven Griph

6674808, Jan 6, 2004

Dec 28, 1999

09/473349

Richard Steven Griph - Mesa AZ
Albert Howard Higashi - Lawrenceville GA

General Dynamics Decision Systems, Inc. - Scottsdale AZ

H04B 1500

375285, 333149

A post-HPA filter rejection equalizer system and method locally equalizes post-HPA filtering. A predistorter ( ) uses a phase error to control the predistortion, and an equalizer ( ) uses a magnitude error to control the equalization. The equalizer samples the HPA output multiple occurrences in a burst fashion. The equalized signal is then used to determine phase and magnitude errors. The phase errors ( ) are used to update the predistorter ( ), and the magnitude errors ( ) are used to update the analytic equalizer.

55286348, Jun 18, 1996

Nov 18, 1993

8/154057

Richard S. Griph - Chandler AZ
Albert H. Higashi - Gilbert AZ

Motorola, Inc. - Schaumburg IL

H04L 700

375354

In a digital demodulator (10) a single sampling moment (28) occurs within each symbol (22). A data estimator (34) identifies a data code and a phase error for each symbol. The data from three symbols (22) are compared to identify whether a phase trajectory is determinate or indeterminate. The phase error from a current symbol is combined with phase trajectory direction data to determine whether a current phase error is in a direction of a next data code or a previous data code. When determinate trajectories are found, phase errors in the direction of a next data code urge the sample moment (28) to occur earlier in the symbols (22) and phase errors in the direction of a previous data code urge the sample moment (28) to occur later in each symbol (22). When indeterminate trajectories are found, substantially no influence is exerted over the timing of the sample moment (28).

60378913, Mar 14, 2000

Feb 23, 1998

9/027759

Richard Steven Griph - Mesa AZ

Motorola, Inc. - Schaumburg IL

H03M 138

341161

A low power serial A/D converter cascades multiple stages (20) of a novel track-and-hold circuit (22) to implement a pipelined A/D converter. The track-and-hold circuit (22) is implemented using a differential structure to cancel out signal droop. This allows extremely high tracking bandwidths to be achieved while maintaining long hold times. Each stage (20) of the pipeline includes a binary quantizing circuit (24) which performs a 1-bit binary estimate of the data and a summing circuit (26) which updates the output of its track-and-hold circuit (22) to allow the next bits to be decided by the following stages.

59907037, Nov 23, 1999

Oct 31, 1997

8/962554

Richard Steven Griph - Mesa AZ

Motorola, Inc. - Schaumburg IL

G05B 100

326 53

A high speed, low power 3-2 adder (300, 500) with latchable outputs comprises a most significant bit (MSB) adder circuit (100) and a least significant bit (LSB) adder circuit (200). MSB adder circuit (100) includes three differential data inputs (A1, B1, and C1), a latch enable input (LE1), three separate bias points, and an MSB output. In addition the LSB adder circuit includes three differential data inputs (A2, B2, and C2), a latch enable input (LE2), three separate bias points and a LSB output. Internal latch circuits (172, 272) and latch enable circuits (174, 274) are provided in each adder stage. Internal latch enable inputs are connected in parallel in one configuration. Separate latch enable inputs are provide in a second configuration. Separate bias points are also provided in each adder stage.