Ravichander C Ledalla

7870515, Jan 11, 2011

Jan 11, 2008

11/972923

Ravichander Ledalla - Fishkill NY, US
Vasant Rao - Fishkill NY, US
Jeffrey P. Soreff - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

G06F 17/50

716 2, 716 4, 716 7, 703 16

A method for hierarchical analysis of electronic circuits comprises selecting a first one of a plurality of abstraction levels of a general design model (GDM). The GDM comprises a first design description of electronic circuits at a plurality of abstraction levels and a plurality of foci, organized into sub-blocks. The method selects a first focus of the plurality of foci to select a first sub-block. The method identifies incomplete electronic circuits in the selected first sub-block. The method generates a second design description of the first sub-block to exclude identified incomplete electronic circuits, wherein the second design description is suitable for electronic design analysis (EDA). The method stores the generated second design description for subsequent use. Subsequent iterations thereby include all components of circuits that were incomplete in prior iterations.

8201120, Jun 12, 2012

Jan 5, 2010

12/652338

Jeffrey P. Soreff - Poughkeepsie NY, US
Barry Lee Dorfman - Austin TX, US
Jeffrey G. Hemmett - St. George VT, US
Ravichander Ledalla - Fishkill NY, US
Vasant Rao - Fishkill NY, US
Fred Lei Yang - Fremont CA, US

International Business Machines Corporation - Armonk NY

G06F 17/50
G06F 9/455

716108, 716113

A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point. It further also applies to interconnect with other two-port parasitic elements, to cases where only a subset of receiver pins on the net require accurate timing, and to cases where a set of electrical nodes, rather than a single node, partition all paths from drivers to receivers on a net.

20040049746, Mar 11, 2004

Sep 6, 2002

10/237328

Vasant Rao - Fishkill NY, US
Ravichander Ledalla - Beacon NY, US
Jeffrey P. Soreff - Poughkeepsie NY, US
Fred Yang - Fremont CA, US

International Business Machine Corporation - Armonk NY

G06F017/50

716/004000, 716/002000, 716/012000, 716/006000

A method for further reducing RC parasitics in an interconnect network following internal node elimination is described. A resistor is initially selected as a candidate for shorting, and it is established whether the accumulated delay error at either end of the resistor is less than a predetermined threshold. This threshold must be a fraction of the time-constant threshold selected by internal node elimination techniques in order to limit the growth of the accumulated delay errors. An important aspect of the invention is the simplicity of the formula used to change the downstream resistor values, namely, the product of the value of the resistor shorted and the ratio of the cumulative downstream capacitances of the two ends of the resistor whose value is being changed. This particular choice of updating the downstream resistor values minimizes the absolute-value of the delay errors at every node due to shorting of the selected resistor. It also preserves the delays at all nodes in the interconnect network apart from the two ends of the resistor selected for shorting.

20180068052, Mar 8, 2018

Nov 14, 2017

15/811826

- Armonk NY, US
Ravichander Ledalla - Fishkill NY, US
Alice H. Lee - Belmont MA, US
Adam P. Matheny - Beacon NY, US
Jose L. Neves - Poughkeepsie NY, US
Gregory M. Schaeffer - Poughkeepsie NY, US

G06F 17/50

An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

20170177784, Jun 22, 2017

Dec 18, 2015

14/973893

- Armonk NY, US
Ravichander Ledalla - Fishkill NY, US
Alice H. Lee - Belmont MA, US
Adam P. Matheny - Beacon NY, US
Jose L. Neves - Poughkeepsie NY, US
Gregory M. Schaeffer - Poughkeepsie NY, US

G06F 17/50

An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

20160314236, Oct 27, 2016

Apr 21, 2015

14/691599

- Hopewell Junction NY, US
Kerim Kalafala - Rhinebeck NY, US
Ravichander Ledalla - Fishkill NY, US
Debjit Sinha - Wappingers Falls NY, US
Chandramouli Visweswariah - Croton-on-Hudson NY, US
Michael H. Wood - Hopewell Junction NY, US

G06F 17/50

The timing analysis of an integrated chip component using dynamic load sensitive timing feedback constraints maintaining the timing accuracy for all the boundary paths is achieved by capturing a reduced order representation for parasitic load within a component for each of its primary input and primary output along with sensitivities of the arrival time, the slew and the required arrival time to the load representation at the component parent level of hierarchy as part of generating load sensitive feedback constraints. During the out-of-context timing closure of the component, the base load representation and the sensitivities, and an updated load representation enables the calculation of the updated boundary constraint for an accurate timing analysis. The accuracy improvement increases a chip designer productivity during timing closure resulting in a shortened time to take the chip design through timing closure to manufacturing. The method is applicable for deterministic as well as for statistical timing analyses.