Ravi K Cherukuri

6393554, May 21, 2002

Jan 19, 2000

09/487771

Stuart F. Oberman - Sunnyvale CA
Ming Siu - San Jose CA
Ravi Krishna Cherukuri - Milpitas CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 752

712221, 708628

A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operands most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booths algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.

6397239, May 28, 2002

Feb 6, 2001

09/778352

Stuart F. Oberman - Sunnyvale CA
Norbert Juffa - San Jose CA
Fred Weber - San Jose CA
Krishnan Ramani - Sunnyvale CA
Ravi Krishna Cherukuri - Milpitas CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 742

708505, 708495

A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder.

6732209, May 4, 2004

Mar 28, 2000

09/536885

Ravi K. Cherukuri - Pleasanton CA
Arun Vaidyanathan - Fremont CA
Viswesh Anathakrishnan - Sunnyvale CA

Juniper Networks, Inc. - Sunnyvale CA

G06F 1338

710240, 710117, 710244, 709240, 370412, 370391

An apparatus and method for distributing data transmission from a plurality of data input queues in a memory buffer to an output. The method includes associating a priority indicator with each data input queue, determining a priority indicator having a highest priority level among the plurality of priority indicators and selecting the data input queue associated with the priority indicator having the highest priority level to transmit to the output.

58782176, Mar 2, 1999

Oct 24, 1997

8/959544

Ravi K. Cherukuri - Fremont CA

Cirrus Logic, Inc. - Fremont CA

G06F 1516
G06F 1200

39520042

A network controller has a default non-DMA mode of data transfer that transfers received data frames to a desired location in internal memory under control of a host CPU. A DMA mode of data transfer is engaged to transfer accumulated data frames via a DMA controller to system memory when the host CPU is not available to handle the frame processing. An automatic switch back mechanism is provided to allow the network controller to automatically switch back to the non-DMA data transfer mode as soon as the host CPU is able to return to processing of received frames.