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Rakesh Mehrotra

from Mesa, AZ
Age ~67
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Also known as:
Rakesh Mehrotre, Rakesh A
Related to:
Rahul MehrotraMohit Mehrotra, 29Anshika Mehrotra, 30Suhani Mehrotra, 34Renu Mehrotra, 63
Connected to:
Amita Mehrotra, 41Anshuman M Mehrotra, 47Atit K Mehrotra, 52Dinesh B Mehrotra, 70Garima Mehrotra, 45Kapil G Mehrotra, 40Maneish Mehrotra, 53Nikhil X Mehrotra, 52Pallavi P Mehrotra, 55Ranjana Mehrotra, 70

Rakesh Mehrotra Phones & Addresses

  • Mesa, AZ
  • Sunnyvale, CA
  • San Jose, CA
  • 1300 Warner Rd, Gilbert, AZ 85233 (480) 813-6803
  • 323 Brisa Dr, Gilbert, AZ 85233 (480) 813-6803
  • Maricopa, AZ
  • 823 W Wagner Ct, Gilbert, AZ 85233

Education

Degree: High school graduate or higher

Business Records

Name / Title
Company / Classification
Phones & Addresses
Rakesh Mehrotra
R & R LAUNDRAMAT, LLC
620 N Hartford, Chandler, AZ 85225
823 W Wagner Ct, Gilbert, AZ 85233
Rakesh Mehrotra
Manager
VEE KAY INTERNATIONAL LLC
Business Services at Non-Commercial Site
823 W Wagner Ct, Gilbert, AZ 85233
823 W Wagoner Ct, Gilbert, AZ 85233

Publications

Us Patents

Memory Architecture

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US Patent:
6400642, Jun 4, 2002
Filed:
Mar 24, 2000
Appl. No.:
09/534671
Inventors:
Rakesh Mehrotra - Santa Clara CA
Pidugu L. Narayana - Sunnyvale CA
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G11C 800
US Classification:
365233, 365221
Abstract:
An apparatus comprising a first memory, a second memory, a control circuit and a flag circuit. The first and second memories may each be configured to store data received from a first data input and present data to a first data output. The control circuit may be configured to control data stored in response to a write clock and control data presented in response to a read clock. The flag circuit may be configured to generate one or more composite flags in response to the first memory and the second memory.

Static Timing Analysis With Simulations On Critical Path Netlists Generated By Static Timing Analysis Tools

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US Patent:
6553549, Apr 22, 2003
Filed:
Feb 10, 2000
Appl. No.:
09/501246
Inventors:
Shiva P. Gowni - Santa Clara CA
Rakesh Mehrotra - Santa Clara CA
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G06F 1750
US Classification:
716 6, 716 4, 716 18, 703 14
Abstract:
A circuit comprising a plurality of gates and a plurality of control circuits. The plurality of gates may each have an output connected to an input of a next gate of the plurality of gates. The plurality of control circuits may be connected to a second input of one or more gates of the plurality of gates. The plurality of control circuits may simulate switching.

Multi-Bit Deskewing Of Bus Signals Using A Training Pattern

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US Patent:
7036037, Apr 25, 2006
Filed:
Aug 13, 2002
Appl. No.:
10/218239
Inventors:
Somnath Paul - Milpitas CA, US
Rakesh Mehrotra - San Jose CA, US
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G06F 1/12
US Classification:
713401, 713503
Abstract:
A method for multi-bit de-skewing of parallel bus signals is disclosed. The method includes receiving data comprising a multi-bit word and a training pattern. After a first control word of the training pattern is detected, the number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of a parallel bus is calculated. The number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of the parallel bus is transmitted to a bit delay line. The system then outputs a de-skewed data word.

Method And System For Providing Hybrid Clock Distribution

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US Patent:
7392495, Jun 24, 2008
Filed:
Aug 13, 2002
Appl. No.:
10/218504
Inventors:
Nagendra Cherukupalli - Cupertino CA, US
Rakesh Mehrotra - San Jose CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 10, 716 8, 716 9, 716 11
Abstract:
A method and system for providing hybrid clock distribution is disclosed. The distribution architecture uses a grid distribution at the top level and a balanced buffer tree distribution at the block level. The method includes determining the block layout of an integrated circuit which employs a clock distribution network for distributing clock signals. In addition the method includes providing a mesh distribution network for delivering clock signals to integrated circuit blocks of the integrated circuit. Thereafter, a balanced tree distribution network for delivering clock signals to the components of each block of the integrated circuit is provided. The top level grid provides predictable min/max skew at the top level and the remainder skew budget can be applied to the blocks.

Method Of Full Semiconductor Chip Timing Closure

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US Patent:
7730437, Jun 1, 2010
Filed:
Oct 24, 2005
Appl. No.:
11/256807
Inventors:
Purushothaman Ramakrishnan - Bangalore, IN
Pattikad Narayanan Ravindran - Bangalor, IN
Chirakkal Varriam Unnikrishnan - Bangalor, IN
Rakesh Mehrotra - San Jose CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 6, 716 4
Abstract:
A method of full semiconductor chip timing closure includes the steps of determining a system level place and route. Next, a static timing analysis for each of a number of subsystems is performed. Finally, a full chip static timing analysis is performed.

Memory Architecture

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US Patent:
62400312, May 29, 2001
Filed:
Mar 24, 2000
Appl. No.:
9/534760
Inventors:
Rakesh Mehrotra - Santa Clara CA
Pidugu L. Narayana - Sunnyvale CA
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G11C 700
US Classification:
365220
Abstract:
An apparatus comprising a first memory and a second memory. The first memory may be configured read and write words from a data stream comprising a plurality of words in response to (i) a first read enable signal and (ii) a first write enable signal. The second memory may be configured to read and write words from the data stream in response to (i) a second read enable signal and (ii) a second write enable signal. The first and second memories may be configured to read and write alternate words of the data stream.
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Rakesh Mehrotra from Mesa, AZ, age ~67 Get Report