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Rajanatha Shettigara

from San Jose, CA
Age ~55
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Also known as:
Rajant Shettigara, Shettigara Rajanatha, Rajanatha A
Phone and address:
3056 Florence Park Dr, San Jose, CA 95135
Related to:
Satish Shettigar, 47Chitra RajanathaChitra Shettigara
Connected to:
Vilas Shettigar, 52Jennifer J Shettleroe, 62Jessica L Shettleroe, 45Leslie A Shettler, 57Stewart T Shettle, 62Abhishek J Shetty, 37Adarsh J Shetty, 36Amarnath V Shetty, 43Ameesha R Shetty, 43Anil K Shetty, 52

Rajanatha Shettigara Phones & Addresses

  • 3056 Florence Park Dr, San Jose, CA 95135
  • 3201 Loma Verde Dr, San Jose, CA 95117
  • 1124 Roewill Dr, San Jose, CA 95117
  • Palm Bay, FL
  • Lubbock, TX
  • Temple, TX
  • Port Richey, FL
  • Sunnyvale, CA
  • Conroe, TX

Work

Company: Kawasaki microelectronics 2009 to Jul 2016 Position: Director of engineering

Skills

Semiconductors • Mixed Signal • Asic • Soc • Electronics • Ic • Embedded Systems • Fpga • Verilog • Consumer Electronics • System Design • Debugging • Signal Integrity • Product Development • Rtl Design • Cross Functional Team Leadership • Vhdl • Laboratory Automation • System Architecture • Characterization • Fiber Optics • Firmware • Program Management • Simulation

Interests

Electronics

Industries

Computer Hardware

Resumes

Resumes

Rajanatha Shettigara Photo 1

Vice President Of Engineering

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Location:
3056 Florence Park Dr, San Jose, CA 95135
Industry:
Computer Hardware
Work:
Kawasaki Microelectronics 2009 - Jul 2016
Director of Engineering
Velodyne Lidar, Inc. 2009 - Jul 2016
Vice President of Engineering
Stmicroelectronics Jan 2008 - Dec 2008
Manager and Principal Engineer
Genesis Microchip Jan 2000 - Jan 2008
Engineering Manager
Arcus Technology India 1996 - 1997
Senior Engineer
Skills:
Semiconductors
Mixed Signal
Asic
Soc
Electronics
Ic
Embedded Systems
Fpga
Verilog
Consumer Electronics
System Design
Debugging
Signal Integrity
Product Development
Rtl Design
Cross Functional Team Leadership
Vhdl
Laboratory Automation
System Architecture
Characterization
Fiber Optics
Firmware
Program Management
Simulation
Interests:
Electronics

Publications

Us Patents

Automatic Fault-Testing Of Logic Blocks Using Internal At-Speed Logic-Bist

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US Patent:
7398443, Jul 8, 2008
Filed:
May 31, 2005
Appl. No.:
11/141763
Inventors:
Venkat Chary Mushirabad - Santa Clara CA, US
Rajanatha Shettigara - Sunnyvale CA, US
Assignee:
Genesis Microchip Inc. - Santa Clara CA
International Classification:
G01R 31/28
US Classification:
714733
Abstract:
System and method for automatic fault-testing of a logic block and the interfaces of macros with logic gates inside a chip, using an at-speed logic-BIST internal to the chip. Following an initialization of internal storage elements, a set of test signals are generated and processed by the logic block. The output of the logic block is accumulated into a signature and compared to a reference signature to detect faults. Testing can be performed on an ATE (Automatic Test Equipment) using a simple test vector, or can be performed by a field engineer on the actual board comprising the chip.

Hybrid Automatic Gain Control (Agc)

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US Patent:
20060089813, Apr 27, 2006
Filed:
Aug 10, 2005
Appl. No.:
11/202417
Inventors:
Sujan Thomas - Sunnyvale CA, US
Rajanatha Shettigara - Sunnyvale CA, US
Assignee:
Genesis Microchip Inc. - Alviso CA
International Classification:
G01B 5/28
G01B 5/30
US Classification:
702039000
Abstract:
A method of automatic gain control in both analog and digital domain is performed by receiving an incoming analog signal, determining an overall gain factor, determining a coarse analog gain control value and a fine digital gain control value, each of which, when taken together substantially equals the already determined overall gain factor, modifying the incoming analog signal using the coarse analog gain control value to form a coarsely adjusted digital signal, digitizing the coarsely adjusted digital signal, and using the fine digital gain control value to process the coarsely adjusted digital signal to form an outgoing digital signal, wherein the outgoing digital signal has been modified in both the analog domain and subsequently in the digital domain to achieve an appropriate signal to noise ratio.

Lidar Signal Acquisition

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US Patent:
20200379094, Dec 3, 2020
Filed:
Aug 6, 2020
Appl. No.:
16/987060
Inventors:
- San Jose CA, US
Rajanatha Shettigara - San Jose CA, US
Nathan Slattengren - San Francisco CA, US
Aaron Chen - Fremont CA, US
Anand Gopalan - Foster City CA, US
International Classification:
G01S 7/4863
G01S 17/89
G01S 7/497
G01S 17/06
G01S 7/484
G01S 17/42
G01S 7/481
G01S 7/486
G01S 7/4865
G01S 17/08
Abstract:
Methods and systems for combining return signals from multiple channels of a LIDAR measurement system are described herein. In one aspect, the outputs of multiple receive channels are electrically coupled before input to a single channel of an analog to digital converter. In another aspect, a DC offset voltage is provided at the output of each transimpedance amplifier of each receive channel to improve measured signal quality. In another aspect, a bias voltage supplied to each photodetector of each receive channel is adjusted based on measured temperature to save power and improve measurement consistency. In another aspect, a bias voltage supplied to each illumination source of each transmit channel is adjusted based on measured temperature. In another aspect, a multiplexer is employed to multiplex multiple sets of output signals of corresponding sets of receive channels before analog to digital conversion.

Lidar Signal Acquisition

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US Patent:
20190178992, Jun 13, 2019
Filed:
Sep 18, 2018
Appl. No.:
16/134000
Inventors:
- Morgan Hill CA, US
Rajanatha Shettigara - San Jose CA, US
Nathan Slattengren - San Francisco CA, US
Aaron Chen - Fremont CA, US
Anand Gopalan - Foster City CA, US
International Classification:
G01S 7/486
G01S 17/89
G01S 17/08
Abstract:
Methods and systems for combining return signals from multiple channels of a LIDAR measurement system are described herein. In one aspect, the outputs of multiple receive channels are electrically coupled before input to a single channel of an analog to digital converter. In another aspect, a DC offset voltage is provided at the output of each transimpedance amplifier of each receive channel to improve measured signal quality. In another aspect, a bias voltage supplied to each photodetector of each receive channel is adjusted based on measured temperature to save power and improve measurement consistency. In another aspect, a bias voltage supplied to each illumination source of each transmit channel is adjusted based on measured temperature. In another aspect, a multiplexer is employed to multiplex multiple sets of output signals of corresponding sets of receive channels before analog to digital conversion.

Data Transmission System

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US Patent:
20190028262, Jan 24, 2019
Filed:
Aug 31, 2018
Appl. No.:
16/119581
Inventors:
- San Jose CA, US
Rajanatha SHETTIGARA - San Jose CA, US
Ramakrishna CHILUKURI - San Jose CA, US
Rahul Kumar AGARWAL - San Jose CA, US
Nobuhiro YANAGISAWA - San Jose CA, US
Sujan Valiyaka THOMAS - San Jose CA, US
Ryuichi MORIIZUMI - San Jose CA, US
Satoru KUMASHIRO - San Jose CA, US
Assignee:
MEGACHIPS TECHNOLOGY AMERICA CORPORATION - San Jose CA
International Classification:
H04L 7/00
H04L 7/033
H04L 7/04
Abstract:
A data transmission method includes, detecting an incoming link training sequence that is transmitted from an upstream transmitter, generating a marker indicating a timing location of a word included in the incoming link training sequence, generating a self link training sequence based on a local reference clock, adjusting a time difference in the incoming link training sequence and the self link training sequence, and retransmitting an incoming bit stream based on the self link training sequence being matched to the incoming link training sequence.
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Rajanatha Shettigara from San Jose, CA, age ~55 Get Report